On Tue, Sep 19, 2023 at 02:49:53PM -0300, Gustavo Sousa wrote:
> Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C
> behavior. If we do not properly reset them, we would miss delivery of
> interrupts if a pending bit is set when enabling IRQs.
>
> As an example, the display part of our probe routine contains paths
> where we wait for vblank interrupts. If a display interrupt was already
> pending when enabling IRQs, we would time out waiting for the vblank.
>
> Avoid the potential issue by clearing GFX_MSTR_IRQ as part of the IRQ
> reset.
>
> BSpec: 50875, 54028
> Signed-off-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 77fb57223465..849dea61fc74 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -214,6 +214,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
>
> + if (gt->type != GT_MEDIA && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 10))
> + intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0);
> +
These bits are more tied to the tile than to the GT (even though i915
still conflates the two concepts a bit), so I'm not sure
gen11_gt_irq_reset is the best place to do this; gen11_gt_irq_reset
should generally be focused on things that are GT-centric in the
hardware sense rather than in the i915 sense. Maybe taking care of this
in dg1_irq_reset() would be a better spot?
Matt
> /* Disable RCS, BCS, VCS and VECS class engines. */
> intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
> --
> 2.42.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
