> -----Original Message----- > From: Nilawar, Badal <badal.nilawar@xxxxxxxxx> > Sent: Friday, September 15, 2023 7:26 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Gupta, Anshuman <anshuman.gupta@xxxxxxxxx>; Vivi, Rodrigo > <rodrigo.vivi@xxxxxxxxx> > Subject: [PATCH] drm/i915/gt: Update RC6 mask for mtl_drpc > > It is seen that for RC6 status register is sometimes setting unused bits > without affecting functionality. So updated the mask with used bits. > As mtl_drpc is debug fs function removing MISSING_CASE from default case. Please add some justification in commit log that like "it does not make sense to panic the system, while reading unsupported C state from the register " > > Cc: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> > Signed-off-by: Badal Nilawar <badal.nilawar@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 - > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +- > 2 files changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > index 357e2f865727..f900cc68d6d9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > @@ -290,7 +290,6 @@ static int mtl_drpc(struct seq_file *m) > seq_puts(m, "RC6\n"); > break; > default: > - MISSING_CASE(REG_FIELD_GET(MTL_CC_MASK, > gt_core_status)); > seq_puts(m, "Unknown\n"); > break; > } > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index a00ff51c681d..71b31d52c646 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -26,7 +26,7 @@ > #define MTL_CAGF_MASK REG_GENMASK(8, 0) > #define MTL_CC0 0x0 > #define MTL_CC6 0x3 > -#define MTL_CC_MASK REG_GENMASK(12, > 9) > +#define MTL_CC_MASK REG_GENMASK(10, > 9) Reviewed-by: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> > > /* RPM unit config (Gen8+) */ > #define RPM_CONFIG0 _MMIO(0xd00) > -- > 2.25.1
