> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville > Syrjala > Sent: Wednesday, June 7, 2023 12:45 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: [PATCH v2 14/19] drm/i915/dsb: Evade transcoder undelayed > vblank when using DSB > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > We want to start the DSB execution from the transcoder's undelayed vblank, so in > order to guarantee atomicity with the all the other mmio register writes we need > to evade both vblanks. > > Note that currently we don't add any vblank delay, so this is effectively a nop. But > in the future when we start to program double buffered registers from the DSB > we'll need to delay the pipe's vblank to provide the register programming > "window2" > for the DSB. Agree with this, looks good. Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_crtc.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c > b/drivers/gpu/drm/i915/display/intel_crtc.c > index 36c9b590a058..ff0ebdf7cde3 100644 > --- a/drivers/gpu/drm/i915/display/intel_crtc.c > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c > @@ -519,8 +519,12 @@ void intel_pipe_update_start(struct intel_crtc_state > *new_crtc_state) > /* > * M/N is double buffered on the transcoder's undelayed vblank, > * so with seamless M/N we must evade both vblanks. > + * > + * DSB execution waits for the transcoder's undelayed vblank, > + * hence we must kick off the commit before that. > */ > - if (new_crtc_state->seamless_m_n && > intel_crtc_needs_fastset(new_crtc_state)) > + if (new_crtc_state->dsb || > + (new_crtc_state->seamless_m_n && > +intel_crtc_needs_fastset(new_crtc_state))) > min -= adjusted_mode->crtc_vblank_start - adjusted_mode- > >crtc_vdisplay; > > if (min <= 0 || max <= 0) > -- > 2.39.3
