| Series: | Enable Lunar Lake display (rev4) |
| URL: | https://patchwork.freedesktop.org/series/122799/ |
| State: | success |
| Details: | https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122799v4/index.html |
CI Bug Log - changes from CI_DRM_13622 -> Patchwork_122799v4
Summary
SUCCESS
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122799v4/index.html
Participating hosts (38 -> 34)
Missing (4): bat-adlm-1 bat-adlp-11 fi-snb-2520m fi-pnv-d510
Known issues
Here are the changes found in Patchwork_122799v4 that come from known issues:
IGT changes
Issues hit
-
igt@i915_selftest@live@migrate:
- bat-dg2-11: PASS -> DMESG-FAIL (i915#7699 / i915#7913)
-
igt@kms_hdmi_inject@inject-audio:
Possible fixes
-
igt@i915_selftest@live@hugepages:
- bat-mtlp-8: DMESG-WARN (i915#9121) -> PASS
-
igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2:
- bat-dg1-5: FAIL (fdo#103375) -> PASS +4 other tests pass
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Build changes
- Linux: CI_DRM_13622 -> Patchwork_122799v4
CI-20190529: 20190529
CI_DRM_13622: 84ba384a9f96d41e3ec3c331feb544e7d39be04d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7480: a8d38db9ac258d7fd71b2cf7607e259a864f95be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_122799v4: 84ba384a9f96d41e3ec3c331feb544e7d39be04d @ git://anongit.freedesktop.org/gfx-ci/linux
Linux commits
1e1053feb7f5 drm/i915/xe2lpd: Update mbus on post plane updates
e4779eb7c078 drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
38eef2ccba5d drm/i915/lnl: Add programming for CDCLK change
46a39070a159 FIXME: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
80b515c2b8bf drm/i915/lnl: Start using CDCLK through PLL
7ef85f209140 drm/i915/lnl: Add CDCLK table
d5126b1c2b0b drm/i915/lnl: Add gmbus/ddc support
9e1eeab5a24b drm/i915/xe2lpd: Extend Wa_15010685871
b2eda0afd2a6 drm/i915/xe2lpd: Add support for HPD
7e3b69869cbc drm/i915/xe2lpd: Enable odd size and panning for planar yuv
739f01362ab5 drm/i915/xe2lpd: Read pin assignment from IOM
68f24924b7fc drm/i915/xe2lpd: Handle port AUX interrupts
36da552e6c3c drm/i915/xe2lpd: Add DC state support
f933713472e0 drm/i915/xe2lpd: Add display power well
29e0a2391a1f drm/i915/xe2lpd: Re-order DP AUX regs
e803dafba256 drm/i915/display: Use _PICK_EVEN_2RANGES() in DP AUX regs
6efdc5a817b0 drm/i915/display: Fix style and conventions for DP AUX regs
3f1bb33ecc7c drm/i915/xe2lpd: Register DE_RRMR has been removed
33b611718a02 drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
abee38178fbe drm/i915/xe2lpd: Move registers to PICA
ff3547808cdb drm/i915/xe2lpd: Move D2D enable/disable
5a518ae3f952 drm/i915/display: Consolidate saved port bits in intel_digital_port
5e4ef9a328fc drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
41e4af2a4ec1 drm/i915/xe2lpd: Add fake PCH
649ed5aabcb0 drm/i915: Re-order if/else ladder in intel_detect_pch()
b547bddccfaf drm/i915/display: Remove FBC capability from fused off pipes
f7b20a7c584f drm/i915/xe2lpd: FBC is now supported on all pipes
8e24e62c5576 drm/i915/lnl: Add display definitions
f9a895c8e4be drm/i915/xelpdp: Add XE_LPDP_FEATURES
