> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville > Syrjala > Sent: Wednesday, June 7, 2023 12:45 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: [PATCH v2 04/19] drm/i915/dsb: Define more DSB bits > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Define all the DSB register bits so I don't have to look through bspec to find them. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_dsb_regs.h | 31 +++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h > b/drivers/gpu/drm/i915/display/intel_dsb_regs.h > index 12535d478775..210e2665441d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h > @@ -37,6 +37,19 @@ > #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + > 0x14) > #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, > id) + 0x1c) > #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + > 0x24) > +#define DSB_HP_IDLE_STATUS REG_BIT(31) > +#define DSB_DEWAKE_STATUS REG_BIT(30) > +#define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27) > +#define DSB_SAFE_WINDOW_LIVE REG_BIT(26) > +#define DSB_VTDFAULT_ARB_SM_STATE_MASK REG_GENMASK(25, 23) > +#define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20) > +#define DSB_SAFE_WINDOW REG_BIT(19) > +#define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17) > +#define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16) > +#define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13) > +#define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7) > +#define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) > +#define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0) > #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, > id) + 0x28) > #define DSB_ATS_FAULT_INT_EN REG_BIT(20) > #define DSB_GTT_FAULT_INT_EN REG_BIT(19) > @@ -58,10 +71,28 @@ > #define DSB_RM_READY_TIMEOUT_VALUE(x) > REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */ > #define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) > _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34) > #define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + > 0x38) > +#define DSB_ENABLE_DEWAKE REG_BIT(31) > +#define DSB_SCANLINE_FOR_DEWAKE_MASK REG_GENMASK(30, 0) > +#define DSB_SCANLINE_FOR_DEWAKE(x) > REG_FIELD_PREP(DSB_SCANLINE_FOR_DEWAKE_MASK, (x)) > #define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, > id) + 0x3c) > +#define DSB_MMIOGEN_DEWAKE_DIS REG_BIT(31) > +#define DSB_FORCE_DEWAKE REG_BIT(23) > +#define DSB_BLOCK_DEWAKE_EXTENSION REG_BIT(15) > +#define DSB_OVERRIDE_DC5_DC6_OK REG_BIT(7) > #define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + > 0x40) > #define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + > 0x44) > #define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + > 0x48) > #define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + > 0xf0) > +#define DSB_FORCE_DMA_SYNC_RESET REG_BIT(31) > +#define DSB_FORCE_VTD_ENGIE_RESET REG_BIT(30) > +#define DSB_DISABLE_IPC_DEMOTE REG_BIT(29) > +#define DSB_SKIP_WAITS_EN REG_BIT(23) > +#define DSB_EXTEND_HP_IDLE REG_BIT(16) > +#define DSB_CTRL_WAIT_SAFE_WINDOW REG_BIT(15) > +#define DSB_CTRL_NO_WAIT_VBLANK REG_BIT(14) > +#define DSB_INST_WAIT_SAFE_WINDOW REG_BIT(7) > +#define DSB_INST_NO_WAIT_VBLANK REG_BIT(6) > +#define DSB_MMIOGEN_DEWAKE_DIS_CHICKEN REG_BIT(2) > +#define DSB_DISABLE_MMIO_COUNT_FOR_INDEXED REG_BIT(0) > > #endif /* __INTEL_DSB_REGS_H__ */ > -- > 2.39.3
