This workaround has two different implementations, one for gen 12 to DG2 and another for DG2 and later. In this patch only GEN12 changes are implemented. BSpec: 11354 v2: - Removed extra parentheses from the condition (Lucas) - Fixed spacing and new line (Lucas) v3: - Fixed commit message. v4: - Only GEN12 changes are kept(Matt Ropper) - Renamed the register bit in define Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@xxxxxxxxx> Reviewed-by: Nemesa Garg <nemesa.garg@xxxxxxxxx> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 0e4c638fcbbf..38f02ef8ed01 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -164,6 +164,8 @@ #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4) #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) #define GEN11_ENABLE_32_PLANE_MODE (1 << 7) +#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8) +#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6) #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 864d41bcf6bb..30aca8d03f6b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -712,6 +712,10 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); + /* Wa_18022495364 */ + wa_masked_en(wal, GEN12_CS_DEBUG_MODE2, + INSTRUCTION_STATE_CACHE_INVALIDATE); + /* * Wa_16011163337 - GS_TIMER * -- 2.34.1
