✓ Fi.CI.BAT: success for drm/i915: VRR, LRR, and M/N stuff (rev2)

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Title: Project List - Patchwork
Patch Details
Series:drm/i915: VRR, LRR, and M/N stuff (rev2)
URL:https://patchwork.freedesktop.org/series/123171/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/index.html

CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123171v2

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123171v2/index.html

Participating hosts (30 -> 40)

Additional (11): fi-kbl-7567u fi-bsw-n3050 fi-cfl-8700k fi-ilk-650 fi-apl-guc fi-kbl-guc fi-hsw-4770 fi-kbl-x1275 fi-cfl-8109u fi-blb-e6850 bat-mtlp-6
Missing (1): fi-snb-2520m

Known issues

Here are the changes found in Patchwork_123171v2 that come from known issues:

IGT changes

Issues hit

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

CI-20190529: 20190529
CI_DRM_13588: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7464: 7464
Patchwork_123171v2: da6378eaa945d44a75141f9d9de5e237edb0e660 @ git://anongit.freedesktop.org/gfx-ci/linux

Linux commits

618abd1aa624 drm/i915: Implement transcoder LRR for TGL+
69a79f9093e4 drm/i915: Assert that VRR is off during vblank evasion if necessary
7f538f53ce42 drm/i915: Update VRR parameters in fastset
7c16c4c2068b drm/i915: Disable VRR during seamless M/N changes
e0078a6d82ff drm/i915: Validate that the timings are within the VRR range
de0a2a1f5499 drm/i915: Relocate is_in_vrr_range()
edb0f293b71d drm/i915: Optimize out redundant M/N updates
f410ec04b6eb drm/i915: Adjust seamless_m_n flag behaviour
f1db3855fbb0 drm/i915: Enable VRR later during fastsets
e46ce6c940f8 drm/i915: Extract intel_crtc_vblank_evade_scanlines()
d0b358304ac3 drm/i915: Change intel_pipe_update_{start, end}() calling convention
d9f254b5adf5 drm/i915: Move psr unlock out from the pipe update critical section


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