In case of a panel that supports DRRS and seamless_m_n, dual refresh rate allows to seamlessly switch to a downclock mode to save power. This is expected to happen seamlessly without a full modeset as in this case we allow the mismatch in mode's crtc clock. With VRR fastset patch series (https://patchwork.freedesktop.org/series/115422/) it allows VRR to be toggled in fastset by pre computing and pre programming VRR parameters irrespective of VRR enabled CRTC state. Now in case of Dual refresh rate (DRR), when we switch to/from downclock mode, crtc_clock changes and these parameters get computed to new values. This patch allows the VRR parameters mismatches in case of seamless_m_n fastset. This will allow Dual refresh rate to throttle seamlessly w/o full modeset. These VRR parameters will need to be reprogrammed to the HW in fastset for DRR + VRR to operate in fastset fashion together. This will be done in follow up patches. This tries to address and clarify the feedback recieved on previous revs (https://patchwork.freedesktop.org/patch/553451/?series=122252&rev=4) Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9154 Cc: Drew Davenport <ddavenport@xxxxxxxxxxxx> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Cc: Sean Paul <seanpaul@xxxxxxxxxxxx> Cc: Jani Nikula <jani.nikula@xxxxxxxxx> Signed-off-by: Manasi Navare <navaremanasi@xxxxxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index db3c26e013e3..26d3d2fe0485 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5387,11 +5387,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, if (!fastset) PIPE_CONF_CHECK_BOOL(vrr.enable); - PIPE_CONF_CHECK_I(vrr.vmin); - PIPE_CONF_CHECK_I(vrr.vmax); - PIPE_CONF_CHECK_I(vrr.flipline); - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); + /* FIXME Handle the VRR + Seamless M N case correctly by + programming these VRR parameters in update_crtc() + */ + if (!fastset || !pipe_config->seamless_m_n) { + PIPE_CONF_CHECK_I(vrr.vmin); + PIPE_CONF_CHECK_I(vrr.vmax); + PIPE_CONF_CHECK_I(vrr.flipline); + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I -- 2.42.0.rc1.204.g551eb34607-goog
