> -----Original Message----- > From: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> > Sent: Thursday, August 24, 2023 4:59 PM > To: Manna, Animesh <animesh.manna@xxxxxxxxx>; intel- > gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH v4 1/6] drm/panelreplay: dpcd register > definition for panelreplay > > On Thu, 24 Aug 2023, Animesh Manna <animesh.manna@xxxxxxxxx> wrote: > > DPCD register definition added to check and enable panel replay > > capability of the sink. > > > > Cc: Jouni Högander <jouni.hogander@xxxxxxxxx> > > Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx> > > --- > > include/drm/display/drm_dp.h | 11 +++++++++++ > > If it touches drm, need to Cc: dri-devel. This is not new. My bad, missed somehow. Will add next time. Regards, Animesh > > BR, > Jani. > > > 1 file changed, 11 insertions(+) > > > > diff --git a/include/drm/display/drm_dp.h > > b/include/drm/display/drm_dp.h index e69cece404b3..a38dc5f1731e > 100644 > > --- a/include/drm/display/drm_dp.h > > +++ b/include/drm/display/drm_dp.h > > @@ -543,6 +543,10 @@ > > /* DFP Capability Extension */ > > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ > > > > +#define DP_PANEL_REPLAY_CAP 0x0b0 > > +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) > > +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > > + > > /* Link Configuration */ > > #define DP_LINK_BW_SET 0x100 > > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ > > @@ -716,6 +720,13 @@ > > #define DP_BRANCH_DEVICE_CTRL 0x1a1 > > # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) > > > > +#define PANEL_REPLAY_CONFIG 0x1b0 > > +# define DP_PANEL_REPLAY_ENABLE (1 << 0) > > +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR (1 << 3) > > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 4) > > +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR (1 << 5) > > +# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) > > + > > #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 > > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define > > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 > > -- > Jani Nikula, Intel Open Source Graphics Center
