> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@xxxxxxxxx>
> Sent: Wednesday, August 23, 2023 8:08 PM
> To: intel-xe@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Lisovskiy, Stanislav <stanislav.lisovskiy@xxxxxxxxx>; Kahola, Mika <mika.kahola@xxxxxxxxx>; De Marchi, Lucas
> <lucas.demarchi@xxxxxxxxx>
> Subject: [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
>
> From: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
>
> Previously we always updated DBuf MBUS CTL and DBUF CTL regs after CDCLK has been changed(CDCLK_CTL), however for Xe2-
> LPD we can't do like that anymore. According to BSpec, we have to first update DBuf regs and then write CDCLK regs, when CDCLK
> is decreased, which we do in post plane.
>
> So now we do CDCLK post plane update only after DBuf regs are written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio
> to be written to DBuf regs).
>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f9eda7ad892e..de813831a5cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7113,7 +7113,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> dev_priv->display.funcs.display->commit_modeset_enables(state);
>
> - if (state->modeset)
> + if (state->modeset && DISPLAY_VER(dev_priv) < 20)
> intel_set_cdclk_post_plane_update(state);
>
> intel_wait_for_vblank_workers(state);
> @@ -7160,6 +7160,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> intel_dbuf_post_plane_update(state);
> intel_psr_post_plane_update(state);
>
> + if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
> + intel_set_cdclk_post_plane_update(state);
> +
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> intel_post_plane_update(state, crtc);
>
> --
> 2.40.1
