On Wed, Aug 23, 2023 at 11:03:42AM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx>
Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
i915 module.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx>
Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
---
.../gpu/drm/i915/display/intel_display_device.c | 15 +++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index f87470da25d0..b853cd0c704a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -727,6 +727,20 @@ static const struct intel_display_device_info xe_lpdp_display = {
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
};
+static const struct intel_display_device_info xe2_lpd_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_crawl = 1,
+ .has_cdclk_squash = 1,
XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
common between Xe_LPD+ and Xe2_LPD. Maybe we should add an
XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
are smaller and it's more obvious what the key changes are with this new
IP?
ack
+
+ .__runtime_defaults.ip.ver = 20,
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).
intention was to only do this after
"drm/i915/xe2lpd: FBC is now supported on all pipes". I guess I can
reorder the patches to bring that one first and fix it.
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
+ BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
+};
+
__diag_pop();
#undef INTEL_VGA_DEVICE
@@ -795,6 +809,7 @@ static const struct {
const struct intel_display_device_info *display;
} gmdid_display_map[] = {
{ 14, 0, &xe_lpdp_display },
+ { 20, 0, &xe2_lpd_display },
};
static const struct intel_display_device_info *
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 07f79b1028e1..96ac9a9cc155 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
+#define IS_LUNARLAKE(dev_priv) 0
As noted on the previous patch, we might be able to drop this completely
if we update the fake PCH and gmbus code to match on display IP. Given
that PCH isn't even involved in south display handling anymore, that
seems like it might be reasonable? If anything, we're more likely to
need to match on PICA ID (which has its own GMD_ID register) than base
platform at some point in the future.
ack
thanks
Lucas De Marchi
Matt
#define IS_METEORLAKE_M(i915) \
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
--
2.40.1
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
