On Fri, 11 Aug 2023, Matt Roper <matthew.d.roper@xxxxxxxxx> wrote:
> On Fri, Aug 11, 2023 at 10:32:14AM +0300, Jani Nikula wrote:
>> On Thu, 10 Aug 2023, Matt Roper <matthew.d.roper@xxxxxxxxx> wrote:
>> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
>> > of these workarounds are actually tied to MTL as a platform; they only
>> > relate to the Xe_LPG graphics IP, regardless of what platform it appears
>> > in. At the moment MTL is the only platform that uses Xe_LPG with IP
>> > versions 12.70 and 12.71, but we can't count on this being true in the
>> > future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead
>> > that is purely based on IP version. IS_GFX_GT_IP_STEP() is also
>> > GT-based rather than device-based, which will help prevent mistakes
>> > where we accidentally try to apply Xe_LPG graphics workarounds to the
>> > Xe_LPM+ media GT and vice-versa.
>> >
>> > v2:
>> > - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
>> > used for both graphics and media IP (and any other kind of GTs that
>> > show up in the future).
>> > v3:
>> > - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani)
>> > - Move macro to intel_gt.h. (Andi)
>> >
>> > Cc: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
>> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
>> > Cc: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>
>> > Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
>> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>> > ---
>> > .../drm/i915/display/skl_universal_plane.c | 5 +-
>> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++--
>> > drivers/gpu/drm/i915/gt/intel_gt.h | 20 +++++++
>> > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 7 ++-
>> > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
>> > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
>> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++---------
>> > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
>> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>> > drivers/gpu/drm/i915/i915_drv.h | 4 --
>> > 10 files changed, 64 insertions(+), 45 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > index ffc15d278a39..d557ecd4e1eb 100644
>> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > @@ -20,6 +20,7 @@
>> > #include "skl_scaler.h"
>> > #include "skl_universal_plane.h"
>> > #include "skl_watermark.h"
>> > +#include "gt/intel_gt.h"
>> > #include "pxp/intel_pxp.h"
>> >
>> > static const u32 skl_plane_formats[] = {
>> > @@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
>> > enum pipe pipe, enum plane_id plane_id)
>> > {
>> > /* Wa_14017240301 */
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
>> > return false;
>> >
>> > /* Wa_22011186057 */
>> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > index a4ff55aa5e55..6187b25b67ab 100644
>> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > @@ -4,9 +4,9 @@
>> > */
>> >
>> > #include "gen8_engine_cs.h"
>> > -#include "i915_drv.h"
>> > #include "intel_engine_regs.h"
>> > #include "intel_gpu_commands.h"
>> > +#include "intel_gt.h"
>> > #include "intel_lrc.h"
>> > #include "intel_ring.h"
>> >
>> > @@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
>> > static int mtl_dummy_pipe_control(struct i915_request *rq)
>> > {
>> > /* Wa_14016712196 */
>> > - if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
>> > + if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>> > u32 *cs;
>> >
>> > /* dummy PIPE_CONTROL + depth flush */
>> > @@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>> > u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>> > {
>> > struct drm_i915_private *i915 = rq->i915;
>> > + struct intel_gt *gt = rq->engine->gt;
>> > u32 flags = (PIPE_CONTROL_CS_STALL |
>> > PIPE_CONTROL_TLB_INVALIDATE |
>> > PIPE_CONTROL_TILE_CACHE_FLUSH |
>> > @@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>> > PIPE_CONTROL_FLUSH_ENABLE);
>> >
>> > /* Wa_14016712196 */
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>> > /* dummy PIPE_CONTROL + depth flush */
>> > cs = gen12_emit_pipe_control(cs, 0,
>> > PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
>> > index 7649a46a36cc..de1bb04c864a 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt.h
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>> > @@ -25,6 +25,26 @@ struct drm_printer;
>> > GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
>> > GRAPHICS_VER_FULL((gt)->i915) <= (until)))
>> >
>> > +/*
>> > + * Check that the GT is a graphics GT with a specific IP version and has
>> > + * a stepping in the range [begin, fixed). The lower stepping bound is
>> > + * inclusive, the upper bound is exclusive (corresponding to the first hardware
>> > + * stepping at which the workaround is no longer needed). E.g.,
>> > + *
>> > + * IS_GFX_GT_IP_STEP(GFX, IP_VER(12, 70), STEP_A0, STEP_B0)
>> > + * IS_GFX_GT_IP_STEP(GFX, IP_VER(12, 71), STEP_B1, STEP_FOREVER)
>> > + *
>> > + * "STEP_FOREVER" can be passed as the upper stepping bound for workarounds
>> > + * that have no "fixed" version for the specified IP version.
>> > + */
>> > +#define IS_GFX_GT_IP_STEP(gt, ipver, begin, fixed) ( \
>> > + BUILD_BUG_ON_ZERO((ipver) < IP_VER(2, 0)) + \
>> > + BUILD_BUG_ON_ZERO((fixed) <= (begin)) + \
>>
>> Why is == not okay?
>
> fixed == begin would be an empty set of steppings and should never
> happen (i.e., the first stepping where you need the WA is also the same
> stepping where you no longer need the WA).
Right. Probably should still get that check in the IS_*_STEP() macros,
and reuse those here instead of open coding the same thing.
>
>>
>> > + ((gt)->type != GT_MEDIA && \
>> > + GRAPHICS_VER_FULL((gt)->i915) == (ipver) && \
>> > + INTEL_GRAPHICS_STEP((gt)->i915) >= (begin) && \
>> > + INTEL_GRAPHICS_STEP((gt)->i915) < (fixed)))
>> > +
>>
>> I'd keep using begin-end or from-until instead of begin-fixed. This
>> check should really agnostic about issues that get fixed.
>>
>> We have macros for checking step ranges, e.g. IS_GRAPHICS_STEP(i915,
>> since, util). They should be used instead of duplicating the
>> condition. And in the previous patch you added IS_GFX_GT_IP_RANGE()
>> which is also pretty much duplicated here?
>>
>> But the stepping check is really orthogonal from the other conditions. I
>> was hoping to replace the IS_MTL_GRAPHICS_STEP() and friends macros with
>> IS_METEORLAKE() && IS_GRAPHICS_STEP() combos, because there's nothing
>> that requires us to keep adding new macros for these.
>
> Part of the goal here is to stop from trying to combine the conditions
> manually because it's too error-prone, and the mistakes tend to slip by
> during code review as well.
>
> * Combining a version range with a stepping range is always a bug.
> * Using a version or version range without checking the GT type is a
> bug on all platforms going forward.
>
> Plus mixing a bunch of && and || conditions makes it easy for typos on
> the parentheses to cause hard-to-spot bugs. The macros here ensure that
> all the conditions that must be combined are always used together
> resulting in a simple || list where each item in the list corresponds to
> one entry in the WA database.
Fair enough. I'd still like to have the building blocks reused here too
instead of open coding in several places.
BR,
Jani.
>
>
> Matt
>
>>
>> Of course, with the IP check there's no need to add new platform
>> specific macros... but is there a need to combine all these together?
>>
>>
>> BR,
>> Jani.
>>
>>
>>
>> > #define GT_TRACE(gt, fmt, ...) do { \
>> > const struct intel_gt *gt__ __maybe_unused = (gt); \
>> > GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> > index 0b414eae1683..11d181b1cc7a 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> > @@ -3,8 +3,7 @@
>> > * Copyright © 2022 Intel Corporation
>> > */
>> >
>> > -#include "i915_drv.h"
>> > -
>> > +#include "intel_gt.h"
>> > #include "intel_gt_mcr.h"
>> > #include "intel_gt_print.h"
>> > #include "intel_gt_regs.h"
>> > @@ -166,8 +165,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>> > gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>> > } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>> > /* Wa_14016747170 */
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>> > fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>> > intel_uncore_read(gt->uncore,
>> > MTL_GT_ACTIVITY_FACTOR));
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > index 957d0aeb0c02..1f0768652446 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > @@ -1375,8 +1375,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>> > cs = gen12_emit_aux_table_inv(ce->engine, cs);
>> >
>> > /* Wa_16014892111 */
>> > - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>> > + if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>> > IS_DG2(ce->engine->i915))
>> > cs = dg2_emit_draw_watermark_setting(cs);
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > index 1ff7b42521c9..fd6c22aeb670 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
>> > if (GRAPHICS_VER(gt->i915) < 11)
>> > return false;
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
>> > return true;
>> >
>> > if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > index 80d67e487b55..e2562b0e540d 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>> > static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>> > struct i915_wa_list *wal)
>> > {
>> > - struct drm_i915_private *i915 = engine->i915;
>> > + struct intel_gt *gt = engine->gt;
>> >
>> > dg2_ctx_gt_tuning_init(engine, wal);
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>> > wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>> > }
>> >
>> > static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>> > struct i915_wa_list *wal)
>> > {
>> > - struct drm_i915_private *i915 = engine->i915;
>> > + struct intel_gt *gt = engine->gt;
>> >
>> > xelpg_ctx_gt_tuning_init(engine, wal);
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>> > /* Wa_14014947963 */
>> > wa_masked_field_set(wal, VF_PREEMPTION,
>> > PREEMPTION_VERTEX_COUNT, 0x4000);
>> > @@ -1747,8 +1747,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>> > /* Wa_22016670082 */
>> > wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>> > /* Wa_14014830051 */
>> > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>> >
>> > @@ -2425,16 +2425,17 @@ static void
>> > rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > {
>> > struct drm_i915_private *i915 = engine->i915;
>> > + struct intel_gt *gt = engine->gt;
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>> > /* Wa_22014600077 */
>> > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>> > ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>> > }
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>> > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>> > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>> > /* Wa_1509727124 */
>> > @@ -2444,7 +2445,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> >
>> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>> > IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
>> > /* Wa_22012856258 */
>> > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>> > GEN12_DISABLE_READ_SUPPRESSION);
>> > @@ -3009,8 +3010,9 @@ static void
>> > general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > {
>> > struct drm_i915_private *i915 = engine->i915;
>> > + struct intel_gt *gt = engine->gt;
>> >
>> > - add_render_compute_tuning_settings(engine->gt, wal);
>> > + add_render_compute_tuning_settings(gt, wal);
>> >
>> > if (GRAPHICS_VER(i915) >= 11) {
>> > /* This is not a Wa (although referred to as
>> > @@ -3031,13 +3033,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>> > GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>> > }
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>> > /* Wa_14017856879 */
>> > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>> > /*
>> > * Wa_14017066071
>> > * Wa_14017654203
>> > @@ -3045,13 +3047,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>> > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>> > MTL_DISABLE_SAMPLER_SC_OOO);
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>> > /* Wa_22015279794 */
>> > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>> > DISABLE_PREFETCH_INTO_IC);
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>> > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>> > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>> > /* Wa_22013037850 */
>> > @@ -3059,16 +3061,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>> > DISABLE_128B_EVICTION_COMMAND_UDW);
>> > }
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>> > IS_PONTEVECCHIO(i915) ||
>> > IS_DG2(i915)) {
>> > /* Wa_22014226127 */
>> > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
>> > }
>> >
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>> > IS_DG2(i915)) {
>> > /* Wa_18017747507 */
>> > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
>> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > index 22649831d3bd..6687cdf0272b 100644
>> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>> > flags |= GUC_WA_GAM_CREDITS;
>> >
>> > /* Wa_14014475959 */
>> > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > IS_DG2(gt->i915))
>> > flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > index 1bd5d8f7c40b..b2150a962f69 100644
>> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>> >
>> > /* Wa_14014475959:dg2 */
>> > if (engine->class == COMPUTE_CLASS)
>> > - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>> > + if (IS_GFX_GT_IP_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > IS_DG2(engine->i915))
>> > engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > index 7a8ce7239bc9..e0e0493d6c1f 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -658,10 +658,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> > #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>> > (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>> >
>> > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>> > - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
>> > - IS_GRAPHICS_STEP(__i915, since, until))
>> > -
>> > #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>> > (IS_METEORLAKE(__i915) && \
>> > IS_DISPLAY_STEP(__i915, since, until))
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
