The patch is tested and the issue is resolved. Thank you. Tested-by: William Tseng <william.tseng@xxxxxxxxx> -----Original Message----- From: Kandpal, Suraj <suraj.kandpal@xxxxxxxxx> Sent: Monday, August 7, 2023 10:28 PM To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Nautiyal, Ankit K <ankit.k.nautiyal@xxxxxxxxx>; Tseng, William <william.tseng@xxxxxxxxx>; Heikkila, Juha-pekka <juha-pekka.heikkila@xxxxxxxxx>; Kandpal, Suraj <suraj.kandpal@xxxxxxxxx> Subject: [PATCH] drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI Assign explicit value of 12 at 8bpp as per Table E2 of DSC 1.1 for DSI panels even though we already use calculations from CModel for first_line_bpg_offset. The reason being some DSI monitors may have not have added the change in errata for the calculation of first_line_bpg_offset. Signed-off-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx> --- drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index f7ebc146f96d..2376d5000d78 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1585,6 +1585,11 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, if (ret) return ret; + /* From Table E-2 in DSC 1.1*/ + if (vdsc_cfg->dsc_version_minor == 1 && + vdsc_cfg->bits_per_pixel == 128) + vdsc_cfg->first_line_bpg_offset = 12; + /* DSI specific sanity checks on the common code */ drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); -- 2.25.1
