Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++------
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7ec8a478e000..f41de126a8d3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1535,6 +1535,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
+static
+u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ return 12;
+ if (DISPLAY_VER(i915) == 11)
+ return 10;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1542,11 +1554,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(i915) >= 12)
- dsc_max_bpc = min_t(u8, 12, max_req_bpc);
- else
- dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+
+ if (!dsc_max_bpc)
+ return dsc_max_bpc;
+
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1674,6 +1687,16 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static
+u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Min DSC Input BPC for ICL+ is 8 */
+ if (DISPLAY_VER(i915) >= 11)
+ return 8;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1707,10 +1730,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_bpp = pipe_config->pipe_bpp;
}
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
+ if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
+ "Computed BPC less than min supported by source for DSC\n");
return -EINVAL;
}
--
2.40.1
