While 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD")
fixes the problem for lane reset logic, there are also more parts of the
implementation that need to take owned PHY lanes into consideration.
This series provides fixes for such places. The changes to the logic
have been tested on a machine with a Type-C connection in DP-Alt mode
using pin assignment D. In that mode, only PHY lane 0 is owned by
display and, without these fixes, we get message bus timeout errors
because we try to perform reads/writes on registers for the not-owned
PHY.
Gustavo Sousa (4):
drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
drm/i915: Simplify intel_cx0_program_phy_lane() with loop
drm/i915/cx0: Enable/disable TX only for owned PHY lanes
drm/i915/cx0: Program vswing only for owned lanes
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 155 ++++++++-----------
1 file changed, 66 insertions(+), 89 deletions(-)
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2.41.0
