Re: [PATCH 2/8] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version

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Quoting Matt Roper (2023-07-18 19:27:56-03:00)
>Although some of our Xe_LPG workarounds were already being applied based
>on IP version correctly, others were matching on MTL as a base platform,
>which is incorrect.  Although MTL is the only platform right now that
>uses Xe_LPG IP, this may not always be the case.  If a future platform
>re-uses this graphics IP, the same workarounds should be applied, even
>if it isn't a "MTL" platform.
>
>We were also incorrectly applying Xe_LPG workarounds/tuning to the
>Xe_LPM+ media IP in one or two places; we should make sure that we don't
>try to apply graphics workarounds to the media GT and vice versa where
>they don't belong.  A new helper macro GT_GRAPHICS_RANGE() is added to
>help ensure this is handled properly -- it checks both the graphics
>version range and that the code isn't operating on a media GT.
>
>Note that many of the stepping-based workarounds are still incorrectly
>checking for a MTL base platform; that will be remedied in a later
>patch.
>
>Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++----------
> drivers/gpu/drm/i915/i915_drv.h             |  5 +++
> 2 files changed, 26 insertions(+), 19 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index b177c588698b..2a5bf50962ad 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>         wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> }
> 
>-static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>-                                   struct i915_wa_list *wal)
>+static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>+                                     struct i915_wa_list *wal)
> {
>         struct drm_i915_private *i915 = engine->i915;
> 
>@@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>                 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> }
> 
>-static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
>-                                     struct i915_wa_list *wal)
>+static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>+                                       struct i915_wa_list *wal)
> {
>         struct drm_i915_private *i915 = engine->i915;
> 
>-        mtl_ctx_gt_tuning_init(engine, wal);
>+        xelpg_ctx_gt_tuning_init(engine, wal);
> 
>         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>             IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>@@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>         if (engine->class != RENDER_CLASS)
>                 goto done;
> 
>-        if (IS_METEORLAKE(i915))
>-                mtl_ctx_workarounds_init(engine, wal);
>+        if (GT_GRAPHICS_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
>+                xelpg_ctx_workarounds_init(engine, wal);
>         else if (IS_PONTEVECCHIO(i915))
>                 ; /* noop; none at this time */
>         else if (IS_DG2(i915))
>@@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  */
> static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> {
>-        if (IS_METEORLAKE(gt->i915)) {
>-                if (gt->type != GT_MEDIA)
>-                        wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>-
>+        if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
>+                wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>                 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
>         }
> 
>@@ -1817,7 +1815,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
>         gt_tuning_settings(gt, wal);
> 
>         if (gt->type == GT_MEDIA) {
>-                if (MEDIA_VER(i915) >= 13)
>+                if (MEDIA_VER(i915) == 13)

This looks a bit unrelated to the commit message. I would add a short note for
this or make it a different patch.

>                         xelpmp_gt_workarounds_init(gt, wal);
>                 else
>                         MISSING_CASE(MEDIA_VER(i915));
>@@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
>                 return;
>         }
> 
>-        if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>+        if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
>                 xelpg_gt_workarounds_init(gt, wal);
>         else if (IS_PONTEVECCHIO(i915))
>                 pvc_gt_workarounds_init(gt, wal);
>@@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
>         blacklist_trtt(engine);
> }
> 
>-static void mtl_whitelist_build(struct intel_engine_cs *engine)
>+static void xelpg_whitelist_build(struct intel_engine_cs *engine)
> {
>         struct i915_wa_list *w = &engine->whitelist;
> 
>@@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> 
>         wa_init_start(w, engine->gt, "whitelist", engine->name);
> 
>-        if (IS_METEORLAKE(i915))
>-                mtl_whitelist_build(engine);
>+        if (engine->gt->type == GT_MEDIA)
>+                ; /* none yet */
>+        else if (GT_GRAPHICS_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
>+                xelpg_whitelist_build(engine);
>         else if (IS_PONTEVECCHIO(i915))
>                 pvc_whitelist_build(engine);
>         else if (IS_DG2(i915))
>@@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  * function invoked by __intel_engine_init_ctx_wa().
>  */
> static void
>-add_render_compute_tuning_settings(struct drm_i915_private *i915,
>+add_render_compute_tuning_settings(struct intel_gt *gt,
>                                    struct i915_wa_list *wal)
> {
>-        if (IS_METEORLAKE(i915) || IS_DG2(i915))
>+        struct drm_i915_private *i915 = gt->i915;
>+
>+        if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
>                 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
> 
>         /*
>@@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> {
>         struct drm_i915_private *i915 = engine->i915;
> 
>-        add_render_compute_tuning_settings(i915, wal);
>+        add_render_compute_tuning_settings(engine->gt, wal);
> 
>         if (GRAPHICS_VER(i915) >= 11) {
>                 /* This is not a Wa (although referred to as
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 682ef2b5c7d5..f38c93d82c56 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -431,6 +431,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> #define IS_GRAPHICS_VER(i915, from, until) \
>         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
> 
>+#define GT_GRAPHICS_RANGE(gt, from, until) \
>+        (BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
>+         ((gt)->type != GT_MEDIA && \
>+          (GRAPHICS_VER_FULL((gt)->i915) >= (from) && GRAPHICS_VER_FULL((gt)->i915) <= (until))))
>+

I know the macro's name is already a bit long, but maybe
s/GT_GRAPHICS_RANGE/IS_GT_GRAPHICS_RANGE/ for consistency?

Considering current discussions on disaggregating macros, wouldn't having macros
IS_GRAPHICS_GT() and IS_GRAPHICS_RANGE() macro be more suitable here?

By the way, I also noticed that the proposed macro uses full versions while
others (e.g. IS_MEDIA_VER) use only the major part. I wonder if we could have a
single way to specify version boundaries so we could reduce the number of
variants. For example, we could have a single IS_GRAPHICS_RANGE() (or
IS_GFX_RANGE?) instead of another one (i.e. IS_GRAPHICS_VER) for comparing only
major ranges. Anyways, this somewhat is out of the scope of this patch, but I
just thought I would mention it.

--
Gustavo Sousa

> #define MEDIA_VER(i915)                        (RUNTIME_INFO(i915)->media.ip.ver)
> #define MEDIA_VER_FULL(i915)                IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
>                                                RUNTIME_INFO(i915)->media.ip.rel)
>-- 
>2.41.0
>




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