> -----Original Message----- > From: Murthy, Arun R <arun.r.murthy@xxxxxxxxx> > Sent: Friday, July 14, 2023 9:37 AM > To: Manna, Animesh <animesh.manna@xxxxxxxxx>; intel- > gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: RE: [PATCH 1/4] drm/i915/panelreplay: dpcd register > definition for panelreplay > > > -----Original Message----- > > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of > > Animesh Manna > > Sent: Thursday, November 10, 2022 8:33 PM > > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > Subject: [PATCH 1/4] drm/i915/panelreplay: dpcd register > > definition for panelreplay > > > > DPCD register definition added to check and enable panel replay > > capability of the sink. > > > > Cc: Jouni Högander <jouni.hogander@xxxxxxxxx> > > Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx> > > --- > > include/drm/display/drm_dp.h | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/include/drm/display/drm_dp.h > > b/include/drm/display/drm_dp.h index e934aab357be..40995f8c2c2f > 100644 > > --- a/include/drm/display/drm_dp.h > > +++ b/include/drm/display/drm_dp.h > > @@ -537,6 +537,10 @@ > > /* DFP Capability Extension */ > > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ > > > > +#define DP_PANEL_REPLAY_CAP 0x0b0 > Per DP2.1 Spec > PANEL_REPLAY_CAP_SUPPORTED 0x0b0 > PANEL_REPLAY_CAP 0x0b1 > > > +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) > > +# define DP_PR_SELECTIVE_UPDATE_SUPPORT (1 << 1) > > + > Instead can BIT() be used here? Thanks Arun for reviewing the changes. Tried to follow similar coding practice overall followed in this file. Regards, Animesh > > Thanks and Regards, > Arun R Murthy > -------------------- > > /* Link Configuration */ > > #define DP_LINK_BW_SET 0x100 > > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ > > @@ -706,6 +710,13 @@ > > #define DP_BRANCH_DEVICE_CTRL 0x1a1 > > # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) > > > > +#define PANEL_REPLAY_CONFIG 0x1b0 > > +# define DP_PANEL_REPLAY_ENABLE (1 << 0) > > +# define DP_PR_UNRECOVERABLE_ERROR (1 << 3) > > +# define DP_PR_RFB_STORAGE_ERROR (1 << 4) > > +# define DP_PR_ACTIVE_FRAME_CRC_ERROR (1 << 5) > > +# define DP_PR_SELECTIVE_UPDATE_ENABLE (1 << 6) > > + > > #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 > > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define > > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 > > -- > > 2.29.0
