> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> Animesh Manna
> Sent: Thursday, November 10, 2022 8:33 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 3/4] drm/i915/panelreplay: Initializaton and
> compute config for panel replay
>
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> Cc: Jouni Högander <jouni.hogander@xxxxxxxxx>
> Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> ---
> .../drm/i915/display/intel_display_types.h | 15 +++++++
> drivers/gpu/drm/i915/display/intel_dp.c | 44 +++++++++++++++----
> drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 4 files changed, 93 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8da87cbb172b..3c126bf47119 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1623,6 +1623,8 @@ struct intel_psr {
> bool irq_aux_error;
> u16 su_w_granularity;
> u16 su_y_granularity;
> + bool source_panel_replay_support;
> + bool sink_panel_replay_support;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> @@ -1926,6 +1928,11 @@ dp_to_lspcon(struct intel_dp *intel_dp) #define
> CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> (intel_dp)->psr.source_support)
>
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> + (intel_dp)-
> >psr.source_panel_replay_support)
> +
> +#define IS_PANEL_REPLAY(intel_dp) (!intel_dp_is_edp(intel_dp))
> +
> static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) {
> if (!intel_encoder_is_dp(encoder))
> @@ -1934,6 +1941,14 @@ static inline bool intel_encoder_can_psr(struct
> intel_encoder *encoder)
> return CAN_PSR(enc_to_intel_dp(encoder));
> }
>
> +static inline bool intel_encoder_can_panel_replay(struct intel_encoder
> +*encoder) {
> + if (!intel_encoder_is_dp(encoder))
> + return false;
> +
> + return CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
> +}
> +
> static inline struct intel_digital_port * hdmi_to_dig_port(struct intel_hdmi
> *intel_hdmi) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7400d6b4c587..25bf18e40b96 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1726,12 +1726,23 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - /*
> - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc->revision = 0x5;
> + if (crtc_state->has_psr && conn_state->connector->connector_type
> !=
> + DRM_MODE_CONNECTOR_eDP) {
> + /*
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> + * Encoding/Colorimetry Format indication.
> + */
> + vsc->revision = 0x7;
> + } else {
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + }
> +
> vsc->length = 0x13;
>
> /* DP 1.4a spec, Table 2-120 */
> @@ -1840,6 +1851,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> vsc->revision = 0x4;
> vsc->length = 0xe;
> }
> + } else if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [Panel Replay with colorimetry info] */
> + intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> + vsc);
> + } else {
> + /*
> + * [Panel Replay without colorimetry info]
> + * Prepare VSC Header for SU as per DP 2.0 spec,
> Table 2-223
> + * VSC SDP supporting 3D stereo + Panel Replay.
> + */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
> } else {
> /*
> * [PSR1]
> @@ -3077,10 +3103,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> drm_dp_vsc_sdp *vsc,
> sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes
> */
>
> /*
> - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> - * per DP 1.4a spec.
> + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format
> as
> + * per DP 1.4a spec and DP 2.0 spec respectively.
> */
> - if (vsc->revision != 0x5)
> + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> goto out;
>
> /* VSC SDP Payload for DB16 through DB18 */ diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index a75b37851504..50394143c798 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -983,6 +983,8 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> &crtc_state->hw.adjusted_mode;
> int psr_setup_time;
>
> + if (CAN_PANEL_REPLAY(intel_dp))
> + goto skip_psr_check;
> /*
> * Current PSR panels don't work reliably with VRR enabled
> * So if VRR is enabled, do not enable PSR.
> @@ -1026,8 +1028,14 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> return;
> }
>
> +skip_psr_check:
> crtc_state->has_psr = true;
> - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> +
> + if (intel_dp_is_edp(intel_dp))
> + crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
> +
> + if (IS_PANEL_REPLAY(intel_dp) && HAS_PSR2_SEL_FETCH(dev_priv))
> + crtc_state->has_psr2 =
> intel_psr2_sel_fetch_config_valid(intel_dp,
> +crtc_state);
>
> crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> @@ -2390,6 +2398,35 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> }
> }
>
> +/**
> + * intel_panel_replay_init - Check for sink and source capability.
> + * @intel_dp: Intel DP
> + *
> + * This function is called after the initializing connector.
> + * (the initializing of connector treats the handling of connector
> +capabilities)
> + * And it initializes basic panel replay stuff for each DP Encoder.
> + */
> +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u8 pr_dpcd = 0;
> +
> + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> + return;
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> +
> + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is not supported by panel\n");
> + return;
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is supported by panel\n");
> + intel_dp->psr.sink_panel_replay_support = true; }
> +
> /**
> * intel_psr_init - Init basic PSR work and mutex.
> * @intel_dp: Intel DP
> @@ -2404,7 +2441,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (!HAS_PSR(dev_priv))
> + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
> return;
Should we continue initialization if PR is supported?
>
> /*
> @@ -2423,6 +2460,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
> }
>
> intel_dp->psr.source_support = true;
> + intel_dp->psr.source_panel_replay_support = true;
>
> /* Set link_standby x link_off defaults */
> if (DISPLAY_VER(dev_priv) < 12)
> @@ -2432,6 +2470,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,
> tgl_dc3co_disable_work);
> mutex_init(&intel_dp->psr.lock);
> +
> + intel_panel_replay_init(intel_dp);
> }
>
> static int psr_get_status_and_error_status(struct intel_dp *intel_dp, diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 2ac3a46cccc5..38e613990418 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -34,6 +34,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits,
> enum fb_op_origin origin);
> void intel_psr_init(struct intel_dp *intel_dp);
> +void intel_panel_replay_init(struct intel_dp *intel_dp);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> --
> 2.29.0
