We need to properly estimate our available BW when DSC is enabled because
this can lead both to need in increasing or decresing CDCLK.
Each DSC engine can process only single pixel at a time thus if only
single DSC engine is enabled, CDCLK is obliged to be equal to pixel clock
(while in non-compressed case it can be usualy lower)
However if we have 2 DSC engines CDCLK can be ~pixel clock / 2 and so on.
Lets do the estimation more properly based on amount of VDSC engines used.
That most likely is going to fix some FIFO underruns, we are currently
having.
Stanislav Lisovskiy (2):
drm/i915: Add helper function for getting number of VDSC engines
drm/i915: Don't rely that 2 VDSC engines are always enough for pixel
rate
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +++++++++++--
drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
3 files changed, 23 insertions(+), 6 deletions(-)
--
2.37.3
