On Friday, June 30, 2023 1:35:02 PM PDT Lucas De Marchi wrote: > v3 of https://patchwork.freedesktop.org/series/119766/ > > Changes from v2: > > - Do not rmw if (clr | set) covers all bits > - Add patch to make sure the set bits are also checked on > wa_*_clr_set() when clr is not a superset. > > Tested on DG2 with intel_reg reading 0xb158 with a busy render engine. > Now it's not losing the upper bit anymore. > > Lucas De Marchi (7): > drm/i915/gt: Move wal_get_fw_for_rmw() > drm/i915/gt: Clear all bits from GEN12_FF_MODE2 > drm/i915/gt: Fix context workarounds with non-masked regs > drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround > drm/i915/gt: Enable read back on XEHP_FF_MODE2 > drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER > drm/i915/gt: Also check set bits in clr_set() > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 129 ++++++++++---------- > 1 file changed, 66 insertions(+), 63 deletions(-) Whole series is now: Reviewed-by: Kenneth Graunke <kenneth@xxxxxxxxxxxxx> Thanks a lot for fixing this, Lucas!
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