Thank You for the fix
Tested-by: Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx>
On Thu, 2023-06-15 at 21:39 -0700, Radhakrishna Sripada wrote:
> Driver does not clear the default SSC for MPLLA. This causes link
> training
> failure when trying to use 10G and 20G rates. Fix the behaviour and
> enable ssc
> only when we really want.
>
> Fixes: 237e7be0bf57 ("drm/i915/mtl: For DP2.0 10G and 20G rates use
> MPLLA")
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> Cc: Clint Taylor <Clinton.A.Taylor@xxxxxxxxx>
> Cc: Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx>
> Cc: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f235df5646ed..1b00ef2c6185 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2434,7 +2434,8 @@ static void intel_program_port_clock_ctl(struct
> intel_encoder *encoder,
>
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE |
> - XELPDP_DDI_CLOCK_SELECT_MASK |
> XELPDP_SSC_ENABLE_PLLB, val);
> + XELPDP_DDI_CLOCK_SELECT_MASK |
> XELPDP_SSC_ENABLE_PLLA |
> + XELPDP_SSC_ENABLE_PLLB, val);
> }
>
> static u32 intel_cx0_get_powerdown_update(u8 lane_mask)
