> -----Original Message-----
> From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@xxxxxxxxx>
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Atwood, Matthew S <matthew.s.atwood@xxxxxxxxx>; Srivatsa, Anusha
> <anusha.srivatsa@xxxxxxxxx>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@xxxxxxxxx>
> Subject: [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and
> graphics step
>
> From: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
>
> Driver refers to the platfrom Alderlake P as ADLP in places and ALDERLAKE_P in
^^^ noyiced I have made a typo 😝 @Bhadane, Dnyaneshwar You can fix the typo and add you S-O-B too with mine in the next spin.
Anusha
> some. Making the consistent change to avoid confusion of the right naming
> convention for the platform.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++----
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 2acfa0435675..831d1258ea3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> dev_priv->display.cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> /* Wa_22011320316:adl-p[a0] */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
> dev_priv->display.cdclk.table =
> adlp_a_step_cdclk_table;
> dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> } else if (IS_ADLP_RPLU(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c6d376d414b8..47fe8311067e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct
> drm_i915_private *i915, struct inte {
> u32 val;
>
> - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
> + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
> pll->info->id != DPLL_ID_ICL_DPLL0)
> return;
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f61d39d2b0fc..00c98c2b4324 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> }
>
> /* Wa_22012278275:adl-p */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
> static const u8 map[] = {
> 2, /* 5 lines */
> 1, /* 6 lines */
> @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp
> *intel_dp,
> return;
>
> /* Wa_16011303918:adl-p */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> return;
>
> /*
> @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> drm_dbg_kms(&dev_priv->drm, "PSR2 not completely
> functional in this stepping\n");
> return false;
> }
> @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
>
> /* Wa_16011303918:adl-p */
> if (crtc_state->vrr.enable &&
> - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR2 not enabled, not compatible with HW stepping
> + VRR\n");
> return false;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 25b06ced9ce7..2458a9ea25ba 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct
> drm_i915_private *i915,
> return false;
>
> /* Wa_22011186057 */
> - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> return false;
>
> if (DISPLAY_VER(i915) >= 11)
> @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct
> drm_i915_private *i915,
> return false;
>
> /* Wa_22011186057 */
> - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> return false;
>
> /* Wa_14013215631 */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3c4a66f1a7ba..08e14cf225b5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -677,11 +677,11 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> (IS_ALDERLAKE_S(__i915) && \
> IS_GRAPHICS_STEP(__i915, since, until))
>
> -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
> +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \
> (IS_ALDERLAKE_P(__i915) && \
> IS_DISPLAY_STEP(__i915, since, until))
>
> -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
> +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \
> (IS_ALDERLAKE_P(__i915) && \
> IS_GRAPHICS_STEP(__i915, since, until))
>
> --
> 2.34.1
