Hi Tejas, On Thu, Jun 01, 2023 at 04:39:59PM +0530, Tejas Upadhyay wrote: > For mtl, workaround suggests that, SW insert a > dummy PIPE_CONTROL prior to PIPE_CONTROL which > contains a post sync: Timestamp or Write Immediate. > > Bspec: 72197 > > V5: > - Remove ret variable - Andi > V4: > - Update commit message, avoid returing cs - Andi/Matt > V3: > - Wrap dummy pipe control stuff in API - Andi > V2: > - Fix kernel test robot warnings > > Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@xxxxxxxxx/ > Reviewed-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@xxxxxxxxx> pushed to drm-intel-gt-next. Thanks, Andi
