On Tue, 2023-05-02 at 17:38 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> On pre-TGL FEC is a port level feature, not a transcoder
> level features, and it's DDI A which doesn't have it, not
> trancodere A.
A couple of typos: "level feature" and "transcoder A".
> Check for the correct thing when determining
> whether FEC is supported or not.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4361c1ac65c3..b27b4fb71ed7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1212,13 +1212,13 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> const struct intel_crtc_state *pipe_config)
> {
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - /* On TGL, FEC is supported on all Pipes */
> if (DISPLAY_VER(dev_priv) >= 12)
> return true;
>
> - if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
> + if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> return true;
>
> return false;
Other than that, looks good:
Reviewed-by: Luca Coelho <luciano.coelho@xxxxxxxxx>
--
Cheers,
Luca.
