On Thu, 18 May 2023, Arun R Murthy <arun.r.murthy@xxxxxxxxx> wrote: > With the enablement of global histogram, upon generation of histogram, > an interrupt is triggered. This patch handles the irq. > > Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> > Signed-off-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx> This needs a rebase I think. > --- > drivers/gpu/drm/i915/i915_irq.c | 6 +++++- > drivers/gpu/drm/i915/i915_reg.h | 5 +++-- > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index e28bfb5f7347..d72fb6d9282d 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -43,6 +43,7 @@ > #include "display/intel_hotplug.h" > #include "display/intel_lpe_audio.h" > #include "display/intel_psr.h" > +#include "display/intel_global_hist.h" > > #include "gt/intel_breadcrumbs.h" > #include "gt/intel_gt.h" > @@ -2765,6 +2766,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > ret = IRQ_HANDLED; > intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); > > + if (iir & GEN9_PIPE_GLOBAL_HIST_EVENT) > + intel_global_hist_irq_handler(dev_priv, pipe); > + > if (iir & GEN8_PIPE_VBLANK) > intel_handle_vblank(dev_priv, pipe); > > @@ -5043,7 +5047,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > struct intel_uncore *uncore = &dev_priv->uncore; > > u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | > - GEN8_PIPE_CDCLK_CRC_DONE; > + GEN8_PIPE_CDCLK_CRC_DONE | GEN9_PIPE_GLOBAL_HIST_EVENT; > u32 de_pipe_enables; > u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); > u32 de_port_enables; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 94d0c8d14d43..546207ac4859 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3887,7 +3887,7 @@ > #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) > #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) > #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) > -#define PIPE_DPST_EVENT_ENABLE (1UL << 23) > +#define PIPE_GLOBAL_HIST_EVENT_ENABLE (1UL << 23) > #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) > #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) > #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) > @@ -3910,7 +3910,7 @@ > #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) > #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) > #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) > -#define PIPE_DPST_EVENT_STATUS (1UL << 7) > +#define PIPE_GLOBAL_HIST_EVENT_STATUS (1UL << 7) > #define PIPE_A_PSR_STATUS_VLV (1UL << 6) > #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) > #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) > @@ -5815,6 +5815,7 @@ > #define GEN8_PIPE_VSYNC (1 << 1) > #define GEN8_PIPE_VBLANK (1 << 0) > #define GEN9_PIPE_CURSOR_FAULT (1 << 11) > +#define GEN9_PIPE_GLOBAL_HIST_EVENT (1 << 12) > #define GEN11_PIPE_PLANE7_FAULT (1 << 22) > #define GEN11_PIPE_PLANE6_FAULT (1 << 21) > #define GEN11_PIPE_PLANE5_FAULT (1 << 20) -- Jani Nikula, Intel Open Source Graphics Center
