While disabling Thunderbolt PLL, we request PLL to be stopped and wait for ACK bit to be cleared. The expected value should be '0' instead of '~XELPDP_TBT_CLOCK_ACK' or otherwise we incorrectly receive dmesg warn "PHY PLL not unlocked in 10us". Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d94127e7448b..c64cf6778627 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2861,9 +2861,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), - XELPDP_TBT_CLOCK_ACK, - ~XELPDP_TBT_CLOCK_ACK, - 10, 0, NULL)) + XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", encoder->base.base.id, encoder->base.name, phy_name(phy)); -- 2.34.1
