> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Juha-Pekka Heikkila
> Sent: Thursday, May 4, 2023 1:28 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 4/4] drm/i915/mtl: Add handling for MTL ccs modifiers
>
> Add Tile4 ccs modifiers w/ auxbuffer handling
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 42 ++++++++++++++++++-
> .../drm/i915/display/skl_universal_plane.c | 22 +++++++++-
> 2 files changed, 61 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index c004f08fcfe1..f9420a68ed3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -157,6 +157,32 @@ struct intel_modifier_desc {
>
> static const struct intel_modifier_desc intel_modifiers[] = {
> {
> + .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
> + .display_ver = { 14, 14 },
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
> +
> + .ccs.packed_aux_planes = BIT(1),
> + .ccs.planar_aux_planes = BIT(2) | BIT(3),
> +
> + FORMAT_OVERRIDE(gen12_ccs_formats),
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
> + .display_ver = { 14, 14 },
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
> +
> + .ccs.packed_aux_planes = BIT(1),
> +
> + FORMAT_OVERRIDE(gen12_ccs_formats),
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC,
> + .display_ver = { 14, 14 },
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
> +
> + .ccs.cc_planes = BIT(2),
> + .ccs.packed_aux_planes = BIT(1),
Nitpick, earlier we have defined order in BIT(1), BIT(2), etc. but here we have BIT(2) defined before BIT(1). Maybe define BIT(1) here before BIT2)?
Otherwise, patch looks ok to me.
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> +
> + FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> + }, {
> .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> .display_ver = { 13, 13 },
> .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, @@ -370,6 +396,14 @@ static bool
> plane_has_modifier(struct drm_i915_private *i915,
> if (!plane_caps_contain_all(plane_caps, md->plane_caps))
> return false;
>
> + /*
> + * Separate AuxCCS and Flat CCS modifiers to be run only on platforms
> + * where supported.
> + */
> + if (intel_fb_is_ccs_modifier(md->modifier) &&
> + HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
> + return false;
> +
> return true;
> }
>
> @@ -489,7 +523,7 @@ static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, in {
> const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
>
> - return check_modifier_display_ver_range(md, 12, 13) &&
> + return check_modifier_display_ver_range(md, 12, 14) &&
> ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); }
>
> @@ -605,6 +639,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> fallthrough;
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> @@ -791,6 +828,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 8ea0598a5a07..f6f760e59c9e 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -789,6 +789,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> PLANE_CTL_CLEAR_COLOR_DISABLE;
> case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> + return PLANE_CTL_TILED_4 |
> + PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> + PLANE_CTL_CLEAR_COLOR_DISABLE;
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> + return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> + return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -2160,6 +2168,11 @@ skl_plane_disable_flip_done(struct intel_plane *plane) static bool skl_plane_has_rc_ccs(struct
> drm_i915_private *i915,
> enum pipe pipe, enum plane_id plane_id) {
> + /* Wa_14017240301 */
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + return false;
> +
> /* Wa_22011186057 */
> if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> return false;
> @@ -2441,12 +2454,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> case PLANE_CTL_TILED_Y:
> plane_config->tiling = I915_TILING_Y;
> if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 14)
> + fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS;
> + else if (DISPLAY_VER(dev_priv) >= 12)
> fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> + if (DISPLAY_VER(dev_priv) >= 14)
> + fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> --
> 2.25.1
