On Wed, 26 Apr 2023, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Define and use the bitmasks for the x/y components > of the skl+ scaler window pos/size registers. > > We stick to the full 16 bits mask here even though the > hardware limits are actually lower. The current (ADL) > hardware maximums are in fact: 14 bits for X size, 13 bits > for X pos, 13 bits for Y size/pos. Yes, that is correct, > X pos has less bits than the X size for some reason. But > that doesn't actually matter for now as we don't currently > even support such wide displays without the use of bigjoiner > (due to max plane width limit). > > v2: Switch back to full 16bit masks since that's what > we use transcoder timign regs and PIPESRC as well > > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/skl_scaler.c | 14 ++++++++------ > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > 2 files changed, 16 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c > index 4437d130293a..1e7c97243fcf 100644 > --- a/drivers/gpu/drm/i915/display/skl_scaler.c > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c > @@ -754,9 +754,9 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) > intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), > PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); > intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), > - x << 16 | y); > + PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); > intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), > - width << 16 | height); > + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); > } > > void > @@ -816,9 +816,9 @@ skl_program_plane_scaler(struct intel_plane *plane, > intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), > PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); > intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), > - (crtc_x << 16) | crtc_y); > + PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); > intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), > - (crtc_w << 16) | crtc_h); > + PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); > } > > static void skl_detach_scaler(struct intel_crtc *crtc, int id) > @@ -880,8 +880,10 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) > size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); > > drm_rect_init(&crtc_state->pch_pfit.dst, > - pos >> 16, pos & 0xffff, > - size >> 16, size & 0xffff); > + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), > + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), > + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), > + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); > > scaler_state->scalers[i].in_use = true; > break; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 530bc961088f..b6f691107571 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4106,12 +4106,20 @@ > #define _PS_WIN_POS_1B 0x68970 > #define _PS_WIN_POS_2B 0x68A70 > #define _PS_WIN_POS_1C 0x69170 > +#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) > +#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) > +#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) > +#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) > > #define _PS_WIN_SZ_1A 0x68174 > #define _PS_WIN_SZ_2A 0x68274 > #define _PS_WIN_SZ_1B 0x68974 > #define _PS_WIN_SZ_2B 0x68A74 > #define _PS_WIN_SZ_1C 0x69174 > +#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) > +#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) > +#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) > +#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) > > #define _PS_VSCALE_1A 0x68184 > #define _PS_VSCALE_2A 0x68284 -- Jani Nikula, Intel Open Source Graphics Center
