On Fri, Apr 28, 2023 at 10:36:17AM +0000, Hogander, Jouni wrote: > On Fri, 2023-04-21 at 15:03 +0300, Ville Syrjala wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Implement WaPsrDPAMaskVBlankInSRD:hsw, which makes the hardware > > generate the extra vblank between link training and first frame > > being transmitted. This is the same thing that's controlled by > > TRANS_CHICKEN[21] on skl+ (but due to the funky double buffering > > it's effectively always at the rest value after DC5 exit). So > > for consistent behaviour we want every platform to generate said > > vblank. BDW is already setting this up correctly. > > I couldn't find this from Bspec. I'll guess you have some offline > documentation? WaPsrDPRSUnmaskVBlankInSRD seems to be in Bspec. Bspec has lost the human readable name at some point. It's still there though as w/a #0503. > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_clock_gating.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c > > b/drivers/gpu/drm/i915/intel_clock_gating.c > > index a27600bc5976..9682323510cd 100644 > > --- a/drivers/gpu/drm/i915/intel_clock_gating.c > > +++ b/drivers/gpu/drm/i915/intel_clock_gating.c > > @@ -562,6 +562,9 @@ static void hsw_init_clock_gating(struct > > drm_i915_private *i915) > > /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ > > intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, > > HSW_FBCQ_DIS); > > > > + /* WaPsrDPAMaskVBlankInSRD:hsw */ > > + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, > > HSW_MASK_VBL_TO_PIPE_IN_SRD); > > + > > /* This is required by WaCatErrorRejectionIssue:hsw */ > > intel_uncore_rmw(&i915->uncore, > > GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, > > 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > > BR, > > Jouni Högander -- Ville Syrjälä Intel
