> -----Original Message-----
> From: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>
> Sent: Friday, April 28, 2023 12:07 PM
> To: Kahola, Mika <mika.kahola@xxxxxxxxx>
> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH 01/13] drm/i915/mtl: C20 PLL programming
>
> Hi Mika,
>
> > +static void intel_c20_pll_program(struct drm_i915_private *i915,
> > + const struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + const struct intel_c20pll_state *pll_state = &crtc_state-
> >cx0pll_state.c20;
> > + bool dp = false;
> > + int lane = crtc_state->lane_count == 4 ? INTEL_CX0_BOTH_LANES :
> INTEL_CX0_LANE0;
> > + bool cntx;
> > + int i;
> > +
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + dp = true;
> > +
> > + /* 1. Read current context selection */
> > + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE) &
> > + PHY_C20_CONTEXT_TOGGLE;
> > +
> > + /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
> > + * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable
> MPLLA.
> > + * Protocol switch is only applicable for MPLLA
> > + */
> > + if (intel_c20_protocol_switch_valid(encoder)) {
> > + for (i = 0; i < 4; i++)
> > + intel_c20_sram_write(i915, encoder->port,
> INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
> > + msleep(4);
>
> can you use usleep_range() here?
I think we should use usleep_range() here. If I remember right, the msleep() is not that accurate.
Thanks for spotting!
-Mika-
>
> Andi
