On Tue, 18 Apr 2023, "Kandpal, Suraj" <suraj.kandpal@xxxxxxxxx> wrote:
>> On Mon, Apr 17, 2023 at 03:25:34PM +0300, Kandpal, Suraj wrote:
>> > >
>> > > On Mon, Apr 17, 2023 at 02:43:25PM +0300, Kandpal, Suraj wrote:
>> > > > > [...]
>> > > > > Adding a non-default enable_timeout to the power well descriptor
>> > > > > would avoid adding more platform checks:
>> > > > >
>> > > > > diff --git
>> > > > > a/drivers/gpu/drm/i915/display/intel_display_power_map.c
>> > > > > b/drivers/gpu/drm/i915/display/intel_display_power_map.c
>> > > > > index 6645eb1911d85..8ca1f34be14c2 100644
>> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
>> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
>> > > > > @@ -1378,13 +1378,18 @@ static const struct i915_power_well_desc
>> xelpd_power_wells_main[] = {
>> > > > > I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx =
>> ICL_PW_CTL_IDX_AUX_C),
>> > > > > I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx =
>> XELPD_PW_CTL_IDX_AUX_D),
>> > > > > I915_PW("AUX_E", &icl_pwdoms_aux_e,
>> > > > > .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
>> > > > > + ),
>> > > > > + .ops = &icl_aux_power_well_ops,
>> > > > > + .fixed_enable_delay = true,
>> > > > > + }, {
>> > > > > + .instances = &I915_PW_INSTANCES(
>> > > > > I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1,
>> .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
>> > > > > I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2,
>> .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
>> > > > > I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3,
>> .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
>> > > > > I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4,
>> .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
>> > > > > ),
>> > > > > .ops = &icl_aux_power_well_ops,
>> > > > > - .fixed_enable_delay = true,
>> > > > > + .enable_timeout = 500,
>> > > > > }, {
>> > > > > .instances = &I915_PW_INSTANCES(
>> > > > > I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1,
>> > > > > .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), diff --git
>> > > > > a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> > > > > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> > > > > index 62bafcbc7937c..930a42c825c36 100644
>> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> > > > > @@ -253,6 +253,7 @@ static void
>> > > > > hsw_wait_for_power_well_enable(struct
>> > > > > drm_i915_private *dev_priv, {
>> > > > > const struct i915_power_well_regs *regs = power_well->desc-
>> >ops->regs;
>> > > > > int pw_idx =
>> > > > > i915_power_well_instance(power_well)->hsw.idx;
>> > > > > + int timeout = power_well->desc->enable_timeout ? : 1;
>> > > > >
>> > > > > /*
>> > > > > * For some power wells we're not supposed to watch the
>> > > > > status bit for @@ -266,7 +267,7 @@ static void
>> > > > > hsw_wait_for_power_well_enable(struct drm_i915_private
>> > > > > *dev_priv,
>> > > > >
>> > > > > /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
>> > > > > if (intel_de_wait_for_set(dev_priv, regs->driver,
>> > > > > - HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
>> > > > > + HSW_PWR_WELL_CTL_STATE(pw_idx),
>> > > > > + timeout)) {
>> > > > > drm_dbg_kms(&dev_priv->drm, "%s power well enable
>> timeout\n",
>> > > > > intel_power_well_name(power_well));
>> > > > >
>> > > > > diff --git
>> > > > > a/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> > > > > b/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> > > > > index ba7cb977e7c7f..fd5acf68503e1 100644
>> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> > > > > @@ -110,6 +110,8 @@ struct i915_power_well_desc {
>> > > > > * Thunderbolt mode.
>> > > > > */
>> > > > > u16 is_tc_tbt:1;
>> > > > > + /* Enable timeout if bigger than the default 1ms. */
>> > > > > + u16 enable_timeout;
>> > > > > };
>> > > > >
>> > > >
>> > > > How would we make sure that this timeout only applies to ADLS in
>> > > > that case as that's whom the workaround is for?
>> > >
>> > > The HSD is for display 13 ADL, that is ADL-P/M/N. The ADL-S power
>> > > wells are described separately in adls_power_wells.
>> >
>> > Right sorry meant ADLP so how do we make sure this is enabled only for
>> > the required Display version
>>
>> It is enabled only for those. xelpd_power_wells_main is used by display 13
>> platforms.
>>
>
> Ohkay got it I can float this version of fix if Jani is okay with this.
Yeah go with what Imre says.
BR,
Jani.
>
> Regards,
> Suraj Kandpal
>
>> > Regards,
>> > Suraj Kandpal
>> > >
>> > > --Imre
--
Jani Nikula, Intel Open Source Graphics Center
