On Thu, 2023-03-16 at 13:13 +0200, Mika Kahola wrote:
> From: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
>
> Unlike previous platforms that used PORT_TX_DFLEXDPSP
> for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
> from which the max_lanes has to be calculated.
>
> Bspec: 50235, 65380
>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> Signed-off-by: Jose Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 30 +++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 5756daac91d9..694d74088980 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -15,6 +15,10 @@
> #include "intel_mg_phy_regs.h"
> #include "intel_tc.h"
>
> +#define DP_PIN_ASSIGNMENT_C 0x3
> +#define DP_PIN_ASSIGNMENT_D 0x4
> +#define DP_PIN_ASSIGNMENT_E 0x5
> +
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> {
> static const char * const names[] = {
> @@ -147,6 +151,29 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> }
>
> +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
This function doesn't really return the pin assignment mask, but the
max lane count derived from that. So could you rename the function to
mtl_tc_port_get_max_lane_count() to better reflect what it really does?
We have an internal patch changing this, so we could just fix it up
here directly instead of sending two separate patches.
--
Cheers,
Luca.
