On 3/29/2023 4:24 PM, Ville Syrjälä wrote:
On Wed, Mar 29, 2023 at 02:37:45PM +0530, Ankit Nautiyal wrote:
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index da1c00ee92fb..0b59c1e53678 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -756,8 +756,9 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) <= 13 ? 24 : 36;
We generally prefer "new -> old" order. So please flip that around.
Noted. Will do this in next version.
u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
Hmm. Why is this using the FEC adjusted clock here?
AFAIU we always use FEC for DP when DSC is enabled, provided sink and
source both support FEC.
Bspec mentions : For cases where FEC is enabled, pixel clock is replaced
by pixel clock/0.972261 in the above calculations.
But it seems in this whole function we need a check for
intel_dp_supports_fec() before using adjusted value.
Regards,
Ankit
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
--
2.25.1
