> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Imre > Deak > Sent: Thursday, March 23, 2023 4:21 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: [PATCH 26/29] drm/i915: Move shared DPLL disabling into > CRTC disable hook > > The spec requires disabling the PLL on TC ports before disconnecting the port's > PHY. Prepare for that by moving the PLL disabling to the CRTC disable hook, > while disconnecting the PHY will be moved to the > post_pll_disable() encoder hook in the next patch. > Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 5a386c7c0bc92..ca024f288ab65 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1905,6 +1905,8 @@ static void ilk_crtc_disable(struct intel_atomic_state > *state, > > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); > intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); > + > + intel_disable_shared_dpll(old_crtc_state); > } > > static void hsw_crtc_disable(struct intel_atomic_state *state, @@ -1923,6 > +1925,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, > intel_encoders_post_disable(state, crtc); > } > > + intel_disable_shared_dpll(old_crtc_state); > + > intel_dmc_disable_pipe(i915, crtc->pipe); } > > @@ -7035,7 +7039,6 @@ static void intel_old_crtc_state_disables(struct > intel_atomic_state *state, > dev_priv->display.funcs.display->crtc_disable(state, crtc); > crtc->active = false; > intel_fbc_disable(crtc); > - intel_disable_shared_dpll(old_crtc_state); > > if (!new_crtc_state->hw.active) > intel_initial_watermarks(state, crtc); > -- > 2.37.1
