On Wed, 2023-03-22 at 16:36 +0200, Ville Syrjälä wrote:
> On Wed, Mar 22, 2023 at 04:20:50PM +0200, Vinod Govindapillai wrote:
> > Wrong offsets are calculated to read QGV point registers. Fix it
> > to read from the correct registers.
> >
> > v2: Avoid magic number and better handling the second bitgroup
> >
> > Bspec: 64602
> >
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx>
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index d22ffd7a32dc..74468ed9dc9d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7724,12 +7724,13 @@ enum skl_power_gate {
> > #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> > #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
> >
> > -#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
> > +#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
> > +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point)
> > * 2 * 0x4)
> > #define MTL_TRCD_MASK REG_GENMASK(31, 24)
> > #define MTL_TRP_MASK REG_GENMASK(23, 16)
> > #define MTL_DCLK_MASK REG_GENMASK(15, 0)
> >
> > -#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2)
> > +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + 4 +
> > (point) * 2 * 0x4)
>
> The normal style is to just do '(point) * 8' and '(point) * 8 + 4'
Thanks Ville. Update and v3 sent
BR
vinod
>
> > #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> > #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> >
> > --
> > 2.34.1
>
