This series adds 2 MTL WA's, 2 patches to fix re-use "DC off" power wells and another patch to sync BIOS and driver for C6 enabling. Haridhar Kalvala (1): drm/i915/mtl: WA to clear RDOP clock gating Madhumitha Tolakanahalli Pradeep (1): drm/i915/mtl: Extend Wa_22011802037 to MTL A-step Matt Roper (2): drm/i915: Use separate "DC off" power well for ADL-P and DG2 drm/i915/mtl: Re-use ADL-P's "DC off" power well Vinay Belgaumkar (1): drm/i915/mtl: Synchronize i915/BIOS on C6 enabling .../i915/display/intel_display_power_map.c | 57 +++++++++++++------ drivers/gpu/drm/i915/gt/intel_rc6.c | 21 +++++++ drivers/gpu/drm/i915/gt/intel_rc6_types.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +- 5 files changed, 67 insertions(+), 19 deletions(-) -- 2.34.1
