On Thu, Mar 16, 2023 at 08:55:01AM +0000, Hogander, Jouni wrote:
> On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > VLV/CHV have an extra register to configure some stereo3d
> > signalling details via DP MSA. Make sure we reset that
> > register to zero (since we don't do any stereo3d stuff).
>
> Maybe add Bspec here? It took me a while to find this documentation.
Bpec + vlv/chv is lost cause. I never even bother looking there.
>
> Can you please check also Bspec: 8125 ?
That's the HSW+ MSA register. Different beast.
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index d95817288966..7b371d2746b5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2139,6 +2139,8 @@ static void valleyview_crtc_enable(struct
> > intel_atomic_state *state,
> >
> > intel_set_pipe_src_size(new_crtc_state);
> >
> > + intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
> > +
> > if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> > intel_de_write(dev_priv, CHV_BLEND(pipe),
> > CHV_BLEND_LEGACY);
> > intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 66b6f451b80a..8f301bf4e2b6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7565,6 +7565,12 @@ enum skl_power_gate {
> > #define PIPE_FLIPDONETIMSTMP(pipe) \
> > _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> > _PIPE_FLIPDONETMSTMP_B)
> >
> > +#define _VLV_PIPE_MSA_MISC_A 0x70048
> > +#define VLV_PIPE_MSA_MISC(pipe) \
> > + _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)
> > +#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
> > +#define
> > VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA
> > MISC1 3:1 */
> > +
> > #define GGC _MMIO(0x108040)
> > #define GMS_MASK REG_GENMASK(15, 8)
> > #define GGMS_MASK REG_GENMASK(7, 6)
>
> BR,
>
> Jouni Högander
--
Ville Syrjälä
Intel
