Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dp.c | 51 +++++++++++--------------
1 file changed, 23 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0333fbbc8e60..d83757f211be 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1018,6 +1018,18 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
return MODE_OK;
}
+static enum drm_mode_status
+intel_dp_hdmi_bw_check(struct intel_dp *intel_dp,
+ int target_clock, int bpc,
+ enum intel_output_format sink_format,
+ bool is_frl)
+{
+ if (is_frl)
+ return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
+
+ return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true);
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -1027,48 +1039,31 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ bool is_frl;
enum intel_output_format sink_format;
+ int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw heck */
- ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
- if (intel_dp->dfp.pcon_max_frl_bw) {
+ is_frl = intel_dp->dfp.pcon_max_frl_bw ? true : false;
- if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- else
- sink_format = INTEL_OUTPUT_FORMAT_RGB;
-
- /* Assume 8bpc for the HDMI2.1 FRL BW check */
- status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
- if (status != MODE_OK) {
- if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
- !drm_mode_is_420_also(info, mode))
- return status;
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
- if (status != MODE_OK)
- return status;
- }
-
- return MODE_OK;
- }
-
- if (intel_dp->dfp.max_dotclock &&
+ if (!is_frl && intel_dp->dfp.max_dotclock &&
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl);
if (status != MODE_OK) {
if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, mode))
return status;
sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl);
+ } else {
if (status != MODE_OK)
return status;
}
--
2.25.1
