Re: [PATCH 1/2] Revert "drm/i915/mtl: Add Wa_14017073508 for SAMedia"

["Nilawar, Badal" <badal.nilawar@xxxxxxxxx>]

On 08-03-2023 20:55, Nilawar, Badal wrote:
> Hi Jani,
>
> On 08-03-2023 16:48, Jani Nikula wrote:
> > On Wed, 08 Mar 2023, Badal Nilawar <badal.nilawar@xxxxxxxxx> wrote:
> > > This reverts commit 8f70f1ec587da0b0d52d768fd8c3defbc5e5b55c.
> >
> > Reverts need a commit message too. The why. The cover letter is not
> > recorded in git history.
>
> I will add commit message.

Is it ok if I squash both the commits?

> Regards,
> Badal
> > BR,
> > Jani.
> >
> > > Signed-off-by: Badal Nilawar <badal.nilawar@xxxxxxxxx>
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_gt_pm.c     | 27 -----------------------
> > >   drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 +----------
> > >   drivers/gpu/drm/i915/i915_reg.h           |  9 --------
> > >   3 files changed, 1 insertion(+), 48 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c 
> > > b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > index 85ae7dc079f2..e02cb90723ae 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > @@ -20,31 +20,10 @@
> > >   #include "intel_rc6.h"
> > >   #include "intel_rps.h"
> > >   #include "intel_wakeref.h"
> > > -#include "intel_pcode.h"
> > >   #include "pxp/intel_pxp_pm.h"
> > >   #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
> > > -static void mtl_media_busy(struct intel_gt *gt)
> > > -{
> > > -    /* Wa_14017073508: mtl */
> > > -    if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> > > -        gt->type == GT_MEDIA)
> > > -        snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
> > > -                  PCODE_MBOX_GT_STATE_MEDIA_BUSY,
> > > -                  PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
> > > -}
> > > -
> > > -static void mtl_media_idle(struct intel_gt *gt)
> > > -{
> > > -    /* Wa_14017073508: mtl */
> > > -    if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> > > -        gt->type == GT_MEDIA)
> > > -        snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
> > > -                  PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
> > > -                  PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
> > > -}
> > > -
> > >   static void user_forcewake(struct intel_gt *gt, bool suspend)
> > >   {
> > >       int count = atomic_read(&gt->user_wakeref);
> > > @@ -92,9 +71,6 @@ static int __gt_unpark(struct intel_wakeref *wf)
> > >       GT_TRACE(gt, "\n");
> > > -    /* Wa_14017073508: mtl */
> > > -    mtl_media_busy(gt);
> > > -
> > >       /*
> > >        * It seems that the DMC likes to transition between the DC 
> > > states a lot
> > >        * when there are no connected displays (no active power 
> > > domains) during
> > > @@ -144,9 +120,6 @@ static int __gt_park(struct intel_wakeref *wf)
> > >       GEM_BUG_ON(!wakeref);
> > >       intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
> > > -    /* Wa_14017073508: mtl */
> > > -    mtl_media_idle(gt);
> > > -
> > >       return 0;
> > >   }
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c 
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> > > index fcf51614f9a4..1adec6de223c 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
> > > @@ -12,20 +12,9 @@
> > >   static bool __guc_rc_supported(struct intel_guc *guc)
> > >   {
> > > -    struct intel_gt *gt = guc_to_gt(guc);
> > > -
> > > -    /*
> > > -     * Wa_14017073508: mtl
> > > -     * Do not enable gucrc to avoid additional interrupts which
> > > -     * may disrupt pcode wa.
> > > -     */
> > > -    if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
> > > -        gt->type == GT_MEDIA)
> > > -        return false;
> > > -
> > >       /* GuC RC is unavailable for pre-Gen12 */
> > >       return guc->submission_supported &&
> > > -        GRAPHICS_VER(gt->i915) >= 12;
> > > +        GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
> > >   }
> > >   static bool __guc_rc_selected(struct intel_guc *guc)
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index f2ce4bde6a68..b177cdeee1ec 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6469,15 +6469,6 @@
> > >   /*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
> > >   #define     PCODE_MBOX_DOMAIN_NONE        0x0
> > >   #define     PCODE_MBOX_DOMAIN_MEDIAFF        0x3
> > > -
> > > -/* Wa_14017210380: mtl */
> > > -#define   PCODE_MBOX_GT_STATE            0x50
> > > -/* sub-commands (param1) */
> > > -#define     PCODE_MBOX_GT_STATE_MEDIA_BUSY    0x1
> > > -#define     PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY    0x2
> > > -/* param2 */
> > > -#define     PCODE_MBOX_GT_STATE_DOMAIN_MEDIA    0x1
> > > -
> > >   #define GEN6_PCODE_DATA                _MMIO(0x138128)
> > >   #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT    8
> > >   #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT    16