>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> > Suraj Kandpal
> > Sent: Wednesday, February 1, 2023 2:38 PM
> > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis@xxxxxxxxx>
> > Subject: [PATCH v10 1/6] drm/i915/gsc: Create GSC request
> > submission mechanism
> >
> > HDCP and PXP will require a common function to allow it to submit
> > commands to the gsc cs. Also adding the gsc mtl header that needs to
> > be added on to the existing payloads of HDCP and PXP.
> >
> > --v4
> > -Seprate gsc load and heci cmd submission into different functions in
> > different files for better scalability [Alan] -Rename gsc address
> > field [Alan]
> >
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
> > Cc: Alan Previn <alan.previn.teres.alexis@xxxxxxxxx>
> > Signed-off-by: Suraj Kandpal<suraj.kandpal@xxxxxxxxx>
> > Reviewed-by: Alan Previn <alan.previn.teres.alexis@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
> > drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h | 1 +
> > .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 94
> > +++++++++++++++++++ .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 45
> > +++++++++
> > 5 files changed, 143 insertions(+)
> > create mode 100644
> > drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> > create mode 100644
> > drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index 918470a04591..482928cffb1c
> > 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -195,6 +195,7 @@ i915-y += \
> > i915-y += \
> > gt/uc/intel_gsc_fw.o \
> > gt/uc/intel_gsc_uc.o \
> > + gt/uc/intel_gsc_uc_heci_cmd_submit.o\
> > gt/uc/intel_guc.o \
> > gt/uc/intel_guc_ads.o \
> > gt/uc/intel_guc_capture.o \
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 2af1ae3831df..454179884801 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -439,6 +439,8 @@
> > #define GSC_FW_LOAD GSC_INSTR(1, 0, 2)
> > #define HECI1_FW_LIMIT_VALID (1 << 31)
> >
> > +#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6)
> > +
> > /*
> > * Used to convert any address to canonical form.
> > * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, diff
> > --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
> > b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
> > index 4b5dbb44afb4..146ac0128f69 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
> > @@ -12,4 +12,5 @@ struct intel_gsc_uc;
> >
> > int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc); bool
> > intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
> > +
>
> This redundant and unrelated change can be dropped.
>
Okay got it,
Regard,
Suraj Kandpal
> > #endif
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> > new file mode 100644
> > index 000000000000..be2424af521d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> > @@ -0,0 +1,94 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2023 Intel Corporation */
> > +
> > +#include "gt/intel_engine_pm.h"
> > +#include "gt/intel_gpu_commands.h"
> > +#include "gt/intel_gt.h"
> > +#include "gt/intel_ring.h"
> > +#include "intel_gsc_uc_heci_cmd_submit.h"
> > +
> > +struct gsc_heci_pkt {
> > + u64 addr_in;
> > + u32 size_in;
> > + u64 addr_out;
> > + u32 size_out;
> > +};
> > +
> > +static int emit_gsc_heci_pkt(struct i915_request *rq, struct
> > +gsc_heci_pkt *pkt) {
> > + u32 *cs;
> > +
> > + cs = intel_ring_begin(rq, 8);
> > + if (IS_ERR(cs))
> > + return PTR_ERR(cs);
> > +
> > + *cs++ = GSC_HECI_CMD_PKT;
> > + *cs++ = lower_32_bits(pkt->addr_in);
> > + *cs++ = upper_32_bits(pkt->addr_in);
> > + *cs++ = pkt->size_in;
> > + *cs++ = lower_32_bits(pkt->addr_out);
> > + *cs++ = upper_32_bits(pkt->addr_out);
> > + *cs++ = pkt->size_out;
> > + *cs++ = 0;
> > +
> > + intel_ring_advance(rq, cs);
> > +
> > + return 0;
> > +}
> > +
> > +int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, u64
> addr_in,
> > + u32 size_in, u64 addr_out,
> > + u32 size_out)
> > +{
> > + struct intel_context *ce = gsc->ce;
> > + struct i915_request *rq;
> > + struct gsc_heci_pkt pkt = {
> > + .addr_in = addr_in,
> > + .size_in = size_in,
> > + .addr_out = addr_out,
> > + .size_out = size_out
> > + };
> > + int err;
> > +
> > + if (!ce)
> > + return -ENODEV;
> > +
> > + rq = i915_request_create(ce);
> > + if (IS_ERR(rq))
> > + return PTR_ERR(rq);
> > +
> > + if (ce->engine->emit_init_breadcrumb) {
> > + err = ce->engine->emit_init_breadcrumb(rq);
> > + if (err)
> > + goto out_rq;
> > + }
> > +
> > + err = emit_gsc_heci_pkt(rq, &pkt);
> > +
> > + if (err)
> > + goto out_rq;
> > +
> > + err = ce->engine->emit_flush(rq, 0);
> > +
> > +out_rq:
> > + i915_request_get(rq);
> > +
> > + if (unlikely(err))
> > + i915_request_set_error_once(rq, err);
> > +
> > + i915_request_add(rq);
> > +
> > + if (!err && i915_request_wait(rq, 0, msecs_to_jiffies(500)) < 0)
> > + err = -ETIME;
> > +
> > + i915_request_put(rq);
> > +
> > + if (err)
> > + drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
> > + "Request submission for GSC heci cmd failed (%d)\n",
> > + err);
> > +
> > + return err;
> > +}
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
> > b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
> > new file mode 100644
> > index 000000000000..cf610dfca7a5
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
> > @@ -0,0 +1,45 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2023 Intel Corporation */
> > +
> > +#ifndef _INTEL_GSC_UC_HECI_CMD_SUBMIT_H_ #define
> > +_INTEL_GSC_UC_HECI_CMD_SUBMIT_H_
> > +
> > +#include <linux/types.h>
> > +
> > +struct intel_gsc_uc;
> > +struct intel_gsc_mtl_header {
> > + u32 validity_marker;
> > +#define GSC_HECI_VALIDITY_MARKER 0xA578875A
> > +
> > + u8 heci_client_id;
> > +#define HECI_MEADDRESS_PXP 17
> > +#define HECI_MEADDRESS_HDCP 18
> > +
> > + u8 reserved1;
> > +
> > + u16 header_version;
> > +#define MTL_GSC_HEADER_VERSION 1
> > +
> > + u64 host_session_handle;
> > + u64 gsc_message_handle;
> > +
> > + u32 message_size; /* lower 20 bits only, upper 12 are reserved */
> > +
> > + /*
> > + * Flags mask:
> > + * Bit 0: Pending
> > + * Bit 1: Session Cleanup;
> > + * Bits 2-15: Flags
> > + * Bits 16-31: Extension Size
> > + */
> > + u32 flags;
> > +
> > + u32 status;
> > +} __packed;
> > +
> > +int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc,
> > + u64 addr_in, u32 size_in,
> > + u64 addr_out, u32 size_out);
> > +#endif
> > --
> > 2.25.1
