✓ Fi.CI.BAT: success for drm/i915/dsi: fix DSS CTL register offsets for TGL+ (rev2)

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Title: Project List - Patchwork
Patch Details
Series:drm/i915/dsi: fix DSS CTL register offsets for TGL+ (rev2)
URL:https://patchwork.freedesktop.org/series/114522/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v2/index.html

CI Bug Log - changes from CI_DRM_12807 -> Patchwork_114522v2

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114522v2/index.html

Participating hosts (36 -> 39)

Additional (3): bat-atsm-1 fi-apl-guc fi-pnv-d510

Known issues

Here are the changes found in Patchwork_114522v2 that come from known issues:

IGT changes

Issues hit

Build changes

CI-20190529: 20190529
CI_DRM_12807: 2b332905a3202e5c218463de58bfa3da55e641e5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7180: b6b1ceb4fc4d8f83a9540e4628a6c2648514bb19 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114522v2: 2b332905a3202e5c218463de58bfa3da55e641e5 @ git://anongit.freedesktop.org/gfx-ci/linux

Linux commits

b37b1a989c02 drm/i915/dsi: fix DSS CTL register offsets for TGL+


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