On Fri, Aug 16, 2013 at 09:20:49AM +0100, Chris Wilson wrote:
> On Mon, May 20, 2013 at 11:15:08AM -0700, Stuart Abercrombie wrote:
> > 90% of core speed (=180MHz dot clock) is too high for 2048x1280 to get
> > pixel doubling on Pineview, which it needs to avoid underruns, so
> > lower this to 85%.
> >
> > Signed-off-by: Stuart Abercrombie <sabercrombie@xxxxxxxxxxxx>
>
> I've not found any rationale in the gen3 bspec describing what the upper
> limit on usuable bw is. Nothing to support the old value nor the new, so
>
> Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>
> And quick before Daniel converts the double-wide tracking to
> pipe_config...
Erhm, we've already fixed this for real in
commit 257a7ffcfaf68718c963db6e9978d1f4f647986b
Author: Daniel Vetter <daniel.vetter@xxxxxxxx>
Date: Fri Jul 26 08:35:42 2013 +0200
drm/i915: fix pnv display core clock readout out
and the fact that the above mentioned mode with a pixelclock of 167MHz is
right at the display core clock of 166MHz (per spec) suggests that even
the 10% margin we currently have is massive overkill.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
