90% of core speed (=180MHz dot clock) is too high for 2048x1280 to get
pixel doubling on Pineview, which it needs to avoid underruns, so
lower this to 85%.
Signed-off-by: Stuart Abercrombie <sabercrombie at chromium.org>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index efe8299..9c924e9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4564,14 +4564,14 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
- /* Enable pixel doubling when the dot clock is > 90% of the (display)
+ /* Enable pixel doubling when the dot clock is > 85% of the (display)
* core speed.
*
* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
* pipe == 0 check?
*/
if (intel_crtc->config.requested_mode.clock >
- dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
+ dev_priv->display.get_display_clock_speed(dev) * 17 / 20)
pipeconf |= PIPECONF_DOUBLE_WIDE;
else
pipeconf &= ~PIPECONF_DOUBLE_WIDE;
--
1.8.2.1
