On Tue, Feb 21, 2023 at 11:34:59PM -0800, Radhakrishna Sripada wrote:
> The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> extended the workaround Wa_16015201720 to MTL. However the registers
> that the original WA implemented moved for MTL.
>
> Implement the workaround with the correct register.
The title is still incorrect. 14015855405 is not a workaround lineage
number; you want Wa_16015201720 as you have in the commit message.
>
> Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> Cc: Matt Atwood <matthew.s.atwood@xxxxxxxxx>
> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 35 ++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++--
> 2 files changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index f70ada2357dc..0e478ede66e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
> }
> }
>
> -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> {
> enum pipe pipe;
>
> - if (DISPLAY_VER(i915) < 13)
> - return;
> -
> /*
> - * Wa_16015201720:adl-p,dg2, mtl
> + * Wa_16015201720:adl-p,dg2
> * The WA requires clock gating to be disabled all the time
> * for pipe A and B.
> * For pipe C and D clock gating needs to be disabled only
> @@ -413,6 +410,34 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> PIPEDMC_GATING_DIS, 0);
> }
>
> +static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +{
> + /*
> + * Wa_14015855405
This number is incorrect as well.
> + * The WA requires clock gating to be disabled all the time
> + * for pipe A and B.
> + * For pipe C and D clock gating needs to be disabled only
> + * during initializing the firmware.
> + * TODO/FIXME: WA deviates wrt. enable/disable for Pipes C, D. Needs recheck.
> + * For now carry-forward the implementation for dg2.
Why are we deviating from the documented workaround? As far as I can
see, there's nothing asking us to do this (on any platform). And why
would we handle enable/disable in a different manner? For that matter,
there's nothing specifically asking us to re-enable clock-gating during
suspend/unload either. We should probably clarify the expectations with
the hardware people before landing this patch.
Matt
> + */
> + if (enable)
> + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
> + MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B |
> + MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D);
> + else
> + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0,
> + MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D, 0);
> +}
> +
> +static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +{
> + if (DISPLAY_VER(i915) >= 14)
> + return mtl_pipedmc_clock_gating_wa(i915, enable);
> + else if (DISPLAY_VER(i915) == 13)
> + return adlp_pipedmc_clock_gating_wa(i915, enable);
> +}
> +
> void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> {
> enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1efa655fb68..7c9ac5b43831 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,9 +1794,13 @@
> * GEN9 clock gating regs
> */
> #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> -#define DARBF_GATING_DIS (1 << 27)
> -#define PWM2_GATING_DIS (1 << 14)
> -#define PWM1_GATING_DIS (1 << 13)
> +#define DARBF_GATING_DIS REG_BIT(27)
> +#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
> +#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
> +#define PWM2_GATING_DIS REG_BIT(14)
> +#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13)
> +#define PWM1_GATING_DIS REG_BIT(13)
> +#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12)
>
> #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
> #define TGL_VRH_GATING_DIS REG_BIT(31)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
