On Tue, Feb 21, 2023 at 09:01:24AM +0000, Tvrtko Ursulin wrote:
>
>
> On 20/02/2023 17:18, Andrea Righi wrote:
> > It seems that commit bc3c5e0809ae ("drm/i915/sseu: Don't try to store EU
> > mask internally in UAPI format") exposed a potential out-of-bounds
> > access, reported by UBSAN as following on a laptop with a gen 11 i915
> > card:
> >
> > UBSAN: array-index-out-of-bounds in drivers/gpu/drm/i915/gt/intel_sseu.c:65:27
> > index 6 is out of range for type 'u16 [6]'
> > CPU: 2 PID: 165 Comm: systemd-udevd Not tainted 6.2.0-9-generic #9-Ubuntu
> > Hardware name: Dell Inc. XPS 13 9300/077Y9N, BIOS 1.11.0 03/22/2022
> > Call Trace:
> > <TASK>
> > show_stack+0x4e/0x61
> > dump_stack_lvl+0x4a/0x6f
> > dump_stack+0x10/0x18
> > ubsan_epilogue+0x9/0x3a
> > __ubsan_handle_out_of_bounds.cold+0x42/0x47
> > gen11_compute_sseu_info+0x121/0x130 [i915]
> > intel_sseu_info_init+0x15d/0x2b0 [i915]
> > intel_gt_init_mmio+0x23/0x40 [i915]
> > i915_driver_mmio_probe+0x129/0x400 [i915]
> > ? intel_gt_probe_all+0x91/0x2e0 [i915]
> > i915_driver_probe+0xe1/0x3f0 [i915]
> > ? drm_privacy_screen_get+0x16d/0x190 [drm]
> > ? acpi_dev_found+0x64/0x80
> > i915_pci_probe+0xac/0x1b0 [i915]
> > ...
> >
> > According to the definition of sseu_dev_info, eu_mask->hsw is limited to
> > a maximum of GEN_MAX_SS_PER_HSW_SLICE (6) sub-slices, but
> > gen11_sseu_info_init() can potentially set 8 sub-slices, in the
> > !IS_JSL_EHL(gt->i915) case.
> >
> > Fix this by reserving up to 8 slots for max_subslices in the eu_mask
> > struct.
> >
> > Reported-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> > Signed-off-by: Andrea Righi <andrea.righi@xxxxxxxxxxxxx>
>
> Looks like bug was probably introduced in:
>
> Fixes: bc3c5e0809ae ("drm/i915/sseu: Don't try to store EU mask internally in UAPI format")
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx> # v6.0+
>
> Adding Matt to cross-check.
Yep, looks like there's one specific SKU of ICL that has 8 subslices
that we overlooked previously.
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>
> Regards,
>
> Tvrtko
>
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index aa87d3832d60..d7e8c374f153 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -27,7 +27,7 @@ struct drm_printer;
> > * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> > * I915_MAX_SS_FUSE_BITS value below).
> > */
> > -#define GEN_MAX_SS_PER_HSW_SLICE 6
> > +#define GEN_MAX_SS_PER_HSW_SLICE 8
> > /*
> > * Maximum number of 32-bit registers used by hardware to express the
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
