On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> On TGL VBLANK.VBLANK_START was the mechanism by which we can
> delay the pipe's internal vblank in relation to the transcoder's
> vblank. On ADL+ that no longer does anything. Instead we must
> now use the new TRANS_SET_CONTEXT_LATENCY register. Program it
> accordingly.
>
> And since VBLANK.VBLANK_START is no longer used by the hardware
> on ADL+ let's just zero it out to make it stand out in register
> dumps. Seeing the zeroed value should hopefully remind people
> to check the other register instead.
The specs are a bit hazy on this one. The patch does what it says on the
box, so
Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++++++++++++---
> 1 file changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1d92a789baab..92306246e907 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2821,12 +2821,14 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> enum pipe pipe = crtc->pipe;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> - u32 crtc_vtotal, crtc_vblank_end;
> + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> int vsyncshift = 0;
>
> /* We need to be careful not to changed the adjusted mode, for otherwise
> * the hw state checker will get angry at the mismatch. */
> + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> crtc_vtotal = adjusted_mode->crtc_vtotal;
> + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> crtc_vblank_end = adjusted_mode->crtc_vblank_end;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -2843,6 +2845,21 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> vsyncshift += adjusted_mode->crtc_htotal;
> }
>
> + /*
> + * VBLANK_START no longer works on ADL+, instead we must use
> + * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
> + */
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
> + crtc_vblank_start - crtc_vdisplay);
> +
> + /*
> + * VBLANK_START not used by hw, just clear it
> + * to make it stand out in register dumps.
> + */
> + crtc_vblank_start = 1;
> + }
> +
> if (DISPLAY_VER(dev_priv) > 3)
> intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
> vsyncshift);
> @@ -2858,10 +2875,10 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>
> intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> - VACTIVE(adjusted_mode->crtc_vdisplay - 1) |
> + VACTIVE(crtc_vdisplay - 1) |
> VTOTAL(crtc_vtotal - 1));
> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> - VBLANK_START(adjusted_mode->crtc_vblank_start - 1) |
> + VBLANK_START(crtc_vblank_start - 1) |
> VBLANK_END(crtc_vblank_end - 1));
> intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> @@ -2949,6 +2966,11 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vtotal += 1;
> adjusted_mode->crtc_vblank_end += 1;
> }
> +
> + if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
> + adjusted_mode->crtc_vblank_start =
> + adjusted_mode->crtc_vdisplay +
> + intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
> }
>
> static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel Open Source Graphics Center
