Series: | drm/i915: Transcoder timing stuff |
URL: | https://patchwork.freedesktop.org/series/113974/ |
State: | success |
Details: | https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/index.html |
CI Bug Log - changes from CI_DRM_12734 -> Patchwork_113974v1
Summary
SUCCESS
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/index.html
Participating hosts (39 -> 37)
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113974v1 that come from known issues:
IGT changes
Possible fixes
-
igt@gem_exec_suspend@basic-s0@smem:
-
igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005: DMESG-FAIL (i915#5334) -> PASS
-
igt@i915_selftest@live@hangcheck:
- fi-skl-guc: DMESG-WARN (i915#8073) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Build changes
- Linux: CI_DRM_12734 -> Patchwork_113974v1
CI-20190529: 20190529
CI_DRM_12734: ffa7027c353c6821636559f42584dd11f527b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113974v1: ffa7027c353c6821636559f42584dd11f527b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
Linux commits
889cd17de917 drm/i915: Remove pointless register read
761aa5806d17 drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
62332cb0192d drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
a0acdae8655d drm/i915: Define transcoder timing register bitmasks
9e57f957ca05 drm/i915: Add local adjusted_mode variable
724998b8ebe7 drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY
31848145a8d2 drm/i915: Define the "unmodified vblank" interrupt bit
f9d9e1e0118b drm/i915: Dump blanking start/end
ee5a419f33be drm/i915: s/PIPECONF/TRANSCONF/
a911344d5fe8 drm/i915: Give CPU transcoder timing registers TRANS_ prefix
476bd003a4bd drm/i915: Flatten intel_ddi_{enable, disable}transcoder_clock()
97391c40a064 drm/i915: Rename intel_ddi{enable, disable}_pipe_clock()