On Wed, 08 Feb 2023, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Subject: *registered
>
> Display WA #1178 calls us to tweak some magic bits when doing AUX
> to an external combo PHY port. Instead of looking to see if the VBT
> has declared such a port (which could in theory even alias with a
> declared eDP port on the same PHY) just check the real situation
> based on the registered encoders.
>
> The only slight chicken vs. egg situation here is during output
> probing. But typically we'd register the eDP ports first and so
> once we get to probe anything external on the combo PHY we have
> already determined if it's eDP or not.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> .../drm/i915/display/intel_display_power_well.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 8710dd41ffd4..56a20bf5825b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -391,6 +391,19 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> +static bool intel_port_is_edp(struct drm_i915_private *i915, enum port port)
> +{
> + struct intel_encoder *encoder;
> +
> + for_each_intel_encoder(&i915->drm, encoder) {
> + if (encoder->type == INTEL_OUTPUT_EDP &&
> + encoder->port == port)
> + return true;
> + }
> +
> + return false;
> +}
> +
> static void
> icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> @@ -416,7 +429,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>
> /* Display WA #1178: icl */
> if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
> - !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
> + !intel_port_is_edp(dev_priv, (enum port)phy)) {
> val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx));
> val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val);
--
Jani Nikula, Intel Open Source Graphics Center
