Write-combining memory allows speculative reads by CPU. ggtt->error_capture is WC mapped to CPU, so CPU/MMU can try to prefetch memory beyond the error_capture, ie it tries to read memory pointed by next PTE in GGTT. If this PTE points to invalid address DMAR errors will occur. This behavior was observed on ADL, RPL, DG2 platforms. To avoid it, guard scratch page should be added after error_capture. Signed-off-by: Andrzej Hajda <andrzej.hajda@xxxxxxxxx> --- This patch tries to diminish plague of DMAR errors present in CI for ADL*, RPL*, DG2 platforms, see for example [1] (grep DMAR). CI is usually tolerant for these errors, so the scale of the problem is not really visible. To show it I have counted lines containing DMAR errors in dmesgs produced by CI for 1st version of the patch: CI_DRM_12680: 626 errors Patchwork_113560v1: 136 errors So we have about 500 DMAR error lines per one CI run due to error_capture. [1]: http://gfx-ci.igk.intel.com/tree/drm-tip/CI_DRM_12678/bat-adln-1/dmesg0.txt v2: - modified commit message (I hope the diagnosis is correct), - added bug checks to ensure scratch is initialized on gen3 platforms. CI produces strange stacktrace for it suggesting scratch[0] is NULL, to be removed after resolving the issue with gen3 platforms. [2]: http://gfx-ci.igk.intel.com/tree/drm-tip/Patchwork_113560v2/fi-blb-e6850/igt@i915_module_load@xxxxxxxxx Regards Andrzej --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 30 ++++++++++++++++++++++++---- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 842e69c7b21e49..79e327003da12f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -503,6 +503,14 @@ static void cleanup_init_ggtt(struct i915_ggtt *ggtt) mutex_destroy(&ggtt->error_mutex); } +static void ggtt_insert_scratch_page(struct i915_ggtt *ggtt, u64 offset) +{ + struct i915_address_space *vm = &ggtt->vm; + + GEM_BUG_ON(!vm->scratch[0]); + vm->insert_page(vm, px_dma(vm->scratch[0]), offset, I915_CACHE_NONE, 0); +} + static int init_ggtt(struct i915_ggtt *ggtt) { /* @@ -551,8 +559,12 @@ static int init_ggtt(struct i915_ggtt *ggtt) * paths, and we trust that 0 will remain reserved. However, * the only likely reason for failure to insert is a driver * bug, which we expect to cause other failures... + * + * Since CPU can perform speculative reads on error capture + * (write-combining allows it) add scratch page after it to + * avoid DMAR errors. */ - ggtt->error_capture.size = I915_GTT_PAGE_SIZE; + ggtt->error_capture.size = 2 * I915_GTT_PAGE_SIZE; ggtt->error_capture.color = I915_COLOR_UNEVICTABLE; if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture)) drm_mm_insert_node_in_range(&ggtt->vm.mm, @@ -562,11 +574,21 @@ static int init_ggtt(struct i915_ggtt *ggtt) 0, ggtt->mappable_end, DRM_MM_INSERT_LOW); } - if (drm_mm_node_allocated(&ggtt->error_capture)) + if (drm_mm_node_allocated(&ggtt->error_capture)) { + u64 start = ggtt->error_capture.start; + u64 end = ggtt->error_capture.start + ggtt->error_capture.size; + u64 i; + + /* + * During error capture, memcpying from the GGTT is triggering a + * prefetch of the following PTE, so fill it with a guard page. + */ + for (i = start + I915_GTT_PAGE_SIZE; i < end; i += I915_GTT_PAGE_SIZE) + ggtt_insert_scratch_page(ggtt, i); drm_dbg(&ggtt->vm.i915->drm, "Reserved GGTT:[%llx, %llx] for use by error capture\n", - ggtt->error_capture.start, - ggtt->error_capture.start + ggtt->error_capture.size); + start, end); + } /* * The upper portion of the GuC address space has a sizeable hole diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 4f436ba7a3c833..dddafc33054971 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -293,7 +293,7 @@ void *__px_vaddr(struct drm_i915_gem_object *p) dma_addr_t __px_dma(struct drm_i915_gem_object *p) { - GEM_BUG_ON(!i915_gem_object_has_pages(p)); + GEM_BUG_ON(!p || !i915_gem_object_has_pages(p)); return sg_dma_address(p->mm.pages->sgl); } -- 2.34.1
