On Mon, 2023-01-30 at 13:22 +0000, Coelho, Luciano wrote: > On Mon, 2023-01-30 at 10:06 +0200, Jouni Högander wrote: > > SEL_FETCH_CTL registers are armed immediately when plane is > > disabled. > > SEL_FETCH_* instances of plane configuration are used when doing > > selective update and normal plane register instances for full > > updates. > > Currently all SEL_FETCH_* registers are written as a part of noarm > > plane configuration. If noarm and arm plane configuration are not > > happening within same vblank we may end up having plane as a part > > of > > selective update before it's PLANE_SURF register is written. > > > > Fix this by splitting plane selective fetch configuration into arm > > and > > noarm versions and call them accordingly. Write SEL_FETCH_CTL in > > arm > > version. > > > > v3: > > - add arm suffix into intel_psr2_disable_plane_sel_fetch > > v2: > > - drop color_plane parameter from arm part > > - dev_priv -> i915 in arm part > > > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> > > Cc: Mika Kahola <mika.kahola@xxxxxxxxx> > > Cc: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx> > > Cc: Luca Coelho <luciano.coelho@xxxxxxxxx> > > Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> > > Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > > --- > > Reviewed-by: Luca Coelho <luciano.coelho@xxxxxxxxx> Thank you, this is now merged. > > -- > Cheers, > Luca.
